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參數(shù)資料
| 型號： | SDC-14535-323 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP32 |
| 封裝： | TDIP-32 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 421K |
| 代理商： | SDC-14535-323 |
3
30
90
150
210
270
330
360
θ
(DEGREES)
CCW
In
Phase
with
RL-RH
of
Converter
and
R2-R1
of
CX.
0
S1-S3 = V
SIN
θ
MAX
S3-S2 = V
SIN(
θ + 120°)
MAX
S2-S1 = V
SIN(
θ + 240°)
MAX
- V
MAX
+ V
MAX
Standard Synchro Control Transmitter (CX) Outputs as a Function of
CCW Rotation From Electrical Zero (EZ)
30
90
150
210
270
330
360
θ
(DEGREES)
CCW
In
Phase
with
RH-RL
of
Converter
and
R2-R4
of
RX.
0
S2-S4 = V
COS
θ
MAX
S1-S3 = V
SIN(
θ)
MAX
- V
MAX
+ V
MAX
Standard Resolver Control Transmitter (RX) Outputs as a Function of
CCW Rotation From Electrical Zero (EZ) With R2-R4 Excited.
FIGURE 2. SYNCHRO AND RESOLVER SIGNALS
DIGITAL INTERFACE
The digital interface circuitry performs three main functions:
1. Latches the output bits during an Inhibit (INH) command
allowing stable data to be read out of the SDC-14532.
2. Furnishes parallel and tri-state data formats.
3. Acts as a buffer between the internal CMOS logic and the
external TTL logic.
Applying an inhibit command will lock the data in the transpar-
ent latch without interfering with the continuous tracking of the
feedback loop. Therefore, the digital angle is always updated,
and the inhibit can be applied for an arbitrary amount of time.
The inhibit transparent latch and the 50 ns delay are part of the
inhibit circuitry. The inhibit circuitry is described in detail the
logic input/output section.
LOGIC INPUT/OUTPUT
Logic outputs consist of 12 or 14 parallel data bits and CON-
VERTER BUSY (CB). All logic outputs are short-circuit proof to
ground and +5 volts. The CB output is a positive, 0.4 to 2 s
pulse. Data changes about 50 ns after the leading edge of the
pulse because of an internal delay. Data is valid 0.2 s after the
leading edge of CB. The angle is determined by the sum of the
bits at logic 1. Digital outputs are three-state and two bytes
wide; bits 1-8 (MSBs) are enabled by the signal EM, bits 9-14
(LSBs) are enable by the signal EL. Outputs are valid (logic 1
or 0) 150 ns max after setting EM or EL low and are high
impedance within 100 ns max of setting EM or EL high. Both
EM and EL are internally pulled-up to +5V at 30 A max.
The inhibit (INH) input locks the transparent latch so the bits will
remain stable while data is being transferred (see FIGURE 1).
The output is stable 0.5 s after INH is driven to logic 0 (see
FIGURE 3). A logic 0 at the T input latches the data, and a logic
1 applied to T will allow the bits to change. The inhibit transpar-
ent latch prevents the transmission of invalid data when there is
an overlap between CB and INH. While the counter is not being
updated, CB is at logic 0 and the INH latch is transparent.
When CB goes to logic 1, the INH latch is locked. If CB occurs
after INH has been applied, the latch will remain locked and its
data will not change until CB returns to logic 0; if INH is applied
during CB, the latch will not lock until the CB pulse is over. The
purpose of the 50 ns delay is to prevent a race condition
between CB and INH where the up-down counter begins to
change as an INH is applied. Whenever an input angle change
occurs, the converter changes the digital angle in 1 LSB steps
and generates a converter busy pulse. Output data change is
initiated by the leading edge of the CB pulse, delayed by 50 ns,
nominal. Valid data is available at the outputs 0.2 s after the
leading edge of CB, see FIGURE 4.
,,
DATA
VALID
0.5
s
ASYNCHROUS TO CB
INH
FIGURE 3. INHIBIT TIMING DIAGRAM
An INH input, regardless of its duration, does not affect the con-
verter update. A simple method of interfacing to a computer
asynchronous to CB is:
(1) Apply INH
(2) Wait 0.5 s, min.
(3) Transfer the data.
(4) Release INH.
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