參數(shù)資料
型號： SDA9255
廠商： SIEMENS AG
英文描述： SRC-Scan Rate Converter SDA9255
中文描述： 鋼骨混凝土掃描頻率轉(zhuǎn)換器SDA9255
文件頁數(shù)： 13/45頁
文件大?。?/td> 225K
代理商： SDA9255
SDA 9255
Semiconductor Group
11
1998-02-01
V-Sync (e.g. Intermetall VPC3200A, output delay: 35 ns). For this application the half
system clock (13.5 MHz) from the frontend should be provided at this pin. In case the
frontend is working at 27.0 MHz with sync signals whose delay time are smaller than
25 ns, this input can be set to low level (SYNCEN =
V
SS
) (e.g. Siemens SDA 9257,
SDA 9206, output delay: 25 ns).
Thus the falling edge of HIN signal is detected when the SYNCEN input is low. The
incoming HIN (and VIN) is sampled with the system clock (LL2CLK = 27.0 MHz). The
register value HSDLY and MCNAPIP (subaddress 0B
H
and 0C
H
,
see description of
I
2
C
Bus
) have to be adjusted in the way that the distance from the falling edge of the HIN to
the first active pixel is correct. The half, quarter and eighth system clock is also shown
in this diagram. They are generated inside the SDA 9255. The half system clock
(LL_CLK = 13.5 MHz) is used to sample the incoming YUV data and run some blocks
inside the SDA 9255. The quarter system clock (LH_CLK = 6.75 MHz) is used to run
some blocks inside the SDA 9255. The eighth system clock (LQ_CLK = 3.375 MHz) is
used to synchronize the 4:1:1 input data stream. The setting of the register HSDLY and
MCNAPIP is explained in
chapter 1
.
The SDA 9255 has a fixed number of active pixels per input line. It is fixed to 720
luminance pixels and 180 chrominance pixels.
2.3.1
In order to have always the same raster of the vertical and horizontal synchronization
signal inside the SDA 9255 it is possible to shift the V-Sync signal. The subaddress 09
H
of the SDA 9255 (VSDLY,
see description of
I
2
C Bus
) controls the shift of the V-Sync.
The user has to know the input sync raster and then the user can adjust the VSDLY
register value in the way that the field identify circuit inside the SDA 9255 can work
properly. The adjustment of the V-Sync can be done in steps of 32 clock periods
(LL2CLK). Thus the delay is also dependent on the system clock frequency. The formula
to calculate the delay is shown below.
Delay of Vertical Input Synchronization Signal
DELAY (VIN to VS_int) = (VSDLY
*
32 + 7 ... 11)
*
T
LL2CLK
where:
VIN:
VS_int:
T
LL2CLK
:
The initial delay (7 ... 11 system clocks) is caused by flip-flops at the input. This delay is
not a fixed number, because a quarter of the system clock (LH_CLK) is used to set the
delay. The phase of the LH_CLK is dependent on the RESET and the SYNCEN
(
see
figure 7
).
An example shows figure 9 (
see chapter 5.3, Internal Vertical Synchronization Signal
(VSINP = 0)
). In this example the falling edge of the VIN signal of field A is at 35
μ
s and
the falling edge of the VS_int signal is at 16
μ
s (both signals are related to the falling
Incoming V-Sync at pin 22; VSDLY: is the register value
Internal V-Sync
System clock period (e.g 1/27.0 MHz = 37.04 ns)
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