參數(shù)資料
型號(hào): SDA5254M
廠商: SIEMENS A G
元件分類: 圖文
英文描述: ICs for Consumer Electronics
中文描述: TELETEXT AND VPS/PDC DECODER, PQFP64
文件頁(yè)數(shù): 107/143頁(yè)
文件大小: 1050K
代理商: SDA5254M
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SDA 525x
Semiconductor Group
107
1998-04-08
Further Details of the PWM Unit
The PWM-output channels are placed as alternate functions to the eight lines of port 1.
P1.0 ... P1.5 contain the 6 output channels with 8-bit resolution and P1.6 ... P1.7 the 2
output channels with 14-bit resolution. Each PWM-channel can be individually switched
between PWM-function and port function.
The six 8-bit compare registers PWCOMP0 – PWCOMP5 are located at SFR-addresses
0F1
H
– 0F6
H
. The two 14-bit compare registers consist each of an 8-bit register
PWCOMP6 or PWCOMP7 and of a six-bit extension register PWEXT6 or PWEXT7, all
located at SFR-addresses 0FA
H
– 0FD
H
. They contain the modulation ratios of the
output signals, which are related to the maximum, defined by the counter’s resolution.
These compare registers are double buffered and a new compare value will only be
taken into the main register, after the next timer overflow or if the PWM-timer is stopped.
The PWM-timer registers located at SFR-address F7 and F9
of the PWM-counter low byte and high byte and can only be read by the CPU. Every
compare register, which is not employed for the PWM-output can be used as an
additional register. This is not allowed for register PWME.
The internal timer of the PWM unit is running as long as at least one PWM-channel is
enabled by the PWM-Enable Register PWME.
H
contain the actual value
Table 24
Effect of PWEXTx-Bits for 14-Bit PWM
PWEXTx
Cycle Number ‘Stretched’
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
no effect
1,3,5,7,...,59,61,63
2,6,10,...,54,58,62
4,12,20,...,52,60
8,24,40,56
16,48
32
no effect
Table 25
Base frequencies
PWM Resolution
8 bit
14 bit
Base Frequency
/ 2
/ 2
f
OSC
CDC
x 64
x 256
f
OSC
CDC
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