參數(shù)資料
型號: SDA5251-2
廠商: SIEMENS A G
元件分類: 圖文
英文描述: ICs for Consumer Electronics
中文描述: TELETEXT DECODER, PDIP52
文件頁數(shù): 88/143頁
文件大小: 1050K
代理商: SDA5251-2
SDA 525x
Semiconductor Group
88
1998-04-08
Watchdog Timer Control Bits
Watchdog Timer Reload
Register
Default after reset: 00
H
(MSB)
WDTREL
SFR-Address 86
H
(LSB)
WDTREL.7 WDTREL.6 WDTREL.5 WDTREL.4 WDTREL.3 WDTREL.2 WDTREL.1 WDTREL.0
WDTREL.7
Prescaler bit. When set, the watchdog is clocked through an
additional divide-by-64 prescaler.
WDTREL.0 -
WDTREL.6
Seven bit reload value for the high-byte of the watchdog timer.
This value is loaded to the WDT when a refresh is triggered by
a consecutive setting of bits WDT and SWDT.
Watchdog Timer Control
Register
Default after reset: 00
H
(MSB)
WDTS
SWDT
WDCON
SFR-Address A7
H
(LSB)
WDTS
Watchdog timer reset flag. If bit WDTS is ‘1’ after reset, the
reset has been initiated by the watchdog timer. After external
reset, WDTS is reset to ‘0’.
SWDT
Watchdog timer start flag. Set to activate the watchdog timer.
When directly set after setting WDT, a watchdog timer refresh
is performed.
WDCON.0 - WDCON.5
Reserved.
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