參數(shù)資料
型號: SDA2516-5
廠商: SIEMENS A G
元件分類: DRAM
英文描述: Nonvolatile Memory 1-Kbit E2PROM
中文描述: 128 X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8
封裝: PLASTIC, DIP-8
文件頁數(shù): 10/12頁
文件大小: 272K
代理商: SDA2516-5
Semiconductor Group
14
SDA 2516-5
Figure 2
Timing Conditions for the
I
2
C Bus (high-speed mode)
*) Note that a transmitter must internally provide at least a hold time to bridge the undefined region (max. 300 ns)
of the falling edge of SCL.
Parameter
Symbol
Limit Values
Unit
min.
max.
Minimum time the bus must be free
before a new transmission can start
t
BUF
t
HD; STA
t
LOW
t
HIGH
4.7
μ
s
μ
s
μ
s
μ
s
Start condition hold time
4.0
Clock low period
4.7
Clock high period
4.0
Start condition set-up time,
only valid for repeated start code
t
SU; STA
t
SU; DAT
t
R
t
F
t
SU; SPO
t
HD; DAT
4.7
μ
s
ns
μ
s
ns
μ
s
Data set-up time
250
Rise time of both the SDA- and SCL-line
1
Fall time of both the SDA- and SCL-line
300
Stop condition set-up time
4.7
Hold time data
0*)
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