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參數(shù)資料
| 型號： | SDA 9280 |
| 廠商： | SIEMENS AG |
| 英文描述： | The Digital Display Processor with Integrated 9-Bit Triple D/A Converter for Enhanced TV Applications(帶有應用于增強型TV的集成的9位三級D/A轉換器的數(shù)字顯示器) |
| 中文描述： | 數(shù)字顯示處理器集成9位三的D / A增強型電視用轉換器（帶有應用于增強型電視的集成的9位三級的D / A轉換器的數(shù)字顯示器） |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 118K |
| 代理商： | SDA 9280 |
Application Note
Semiconductor Group
302
The Digital Display Processor SDA 9280 with Integrated 9-Bit Triple
D/A Converter for Enhanced TV Applications
Abstract
The described single IC performs processing and a 9-bit DA conversion of video component
signals. It accepts multiple input data formats and improves picture quality by luminance peaking
filtering, digital chrominance transition improvement and oversampling techniques. Display format
control (4:3, 16:9, …) is realized by time compression or expansion.
Summary
Cost-reduction of TV systems by reduction of the analog application requirements, coupled with an
improvement of the picture quality can be achieved by extended digital signal processing. Some of
this DSP possibilities, being combined with on-chip D/A conversion have been implemented in the
presented display processor in a 1-
μ
m CMOS technology with two layer metallization. The chip has
an area of 50.17 mm
2
, containing 179397 transistors. Most of the used registers are of a dynamic
8-transistor type. The IC is completely controlled by
I
2
C Bus.
The possible input data formats are 4:1:1, 4:2:2 parallel, CCIR 656 and 4:4:4 with 8-bit word length.
The maximal input clock frequency is 30 MHz. For internal processing the chrominance data of
other formats are interpolated to the 4:4:4 parallel format by two interpolation filters (interpolator 1).
Each filter performs a two fold oversampling.
A luminance peaking filter improves the over all frequency response of the luminance channel. It
consists of three filters working in parallel. They have lowpass, bandpass and highpass
characteristics and are separately programmable. An amplification of up to 14 dB at the half of the
sample frequency is available.
A new digital algorithm has been implemented to improve transitions of the chrominance signals,
resulting in a better picture sharpness. A slow change from one color to another because of small
chrominance bandwidth is replaced by a steep transition. Two bandwidth optimized paths are
implemented to detect the position of a color transition in the incoming chrominance signals. The
better suited path is chosen automatically. The sensitivity of this Digital Color Transition
Improvement (DCTI) circuit is programmable.
A compander for time-compression or time-expansion enables a display of signals having different
display formats with correct geometric proportions, e.g. 4:3 signals on 16:9 screens or 16:9 signals
on 4:3 screens. The horizontal compression or expansion of the video signals is performed by
raising or reducing the sample frequency. The data is written into a memory using the system clock
and read with a clock of higher or lower frequency. The compander is a FIFO memory with a storage
capacity of 28 x 188 = 5264 bits implemented as a two-pointer controlled DRAM with dynamic
three-transistor memory cells. The operation frequency of the compander is reduced to maximal
10 MHz by 4-bit parallel-conversion of the serial input write data and parallel-serial-conversion of
the output read data.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SDA9280B22 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:ICs for Consumer Electronics |
| SDA9288 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:畫ˉ中畫/畫外畫處理集成電 |
| SDA9288X | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Single Chip PIP System |
| SDA9288XE-B121 | 制造商:Siemens 功能描述:PICTURE-IN-PICTURE IC, PDSO32 |
| SDA9290-5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Picture Processor |
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