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參數(shù)資料
| 型號(hào)： | SD80C32XXX-36/883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 36 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | 0.600 INCH, CERAMIC, DIP-40 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大小： | 194K |
| 代理商： | SD80C32XXX-36/883 |
6
42073AS-MCU Wireless-02/13
ATmega2564/1284/644RFR2
source current if the pull-up resistors are activated. The Port E pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
Due to the low pin count of the QFN48 package port E6 is not connected to a pin.
Port
E
also
provides
functions
of
various
special
features
of
the
ATmega2564/1284/644RFR2.
3.2.10 Port F (PF7..PF5,PF4/3,PF2...PF0)
Internally Port F is an 8-bit bi-directional I/O port with internal pull-up resistors (selected
for each bit). The Port F output buffers have symmetrical drive characteristics with both
high sink and source capability. As inputs, Port F pins that are externally pulled low will
source current if the pull-up resistors are activated. The Port F pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
Due to the low pin count of the QFN48 package port F3 and F4 are connected to the
same pin. The I/O configuration should be done carefully in order to avoid excessive
power dissipation.
Port
F
also
provides
functions
of
various
special
features
of
the
ATmega2564/1284/644RFR2.
3.2.11 Port G (PG4,PG3,PG1)
Internally Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected
for each bit). The Port G output buffers have symmetrical drive characteristics with both
high sink and source capability. However the driver strength of PG3 and PG4 is
reduced compared to the other port pins. The output voltage drop (VOH, VOL) is higher
while the leakage current is smaller. As inputs, Port G pins that are externally pulled low
will source current if the pull-up resistors are activated. The Port G pins are tri-stated
when a reset condition becomes active, even if the clock is not running.
Due to the low pin count of the QFN48 package port G0, G2 and G5 are not connected
to a pin.
Port
G
also
provides
functions
of
various
special
features
of
the
ATmega2564/1284/644RFR2.
3.2.12 AVSS_RFP
AVSS_RFP is a dedicated ground pin for the bi-directional, differential RF I/O port.
3.2.13 AVSS_RFN
AVSS_RFN is a dedicated ground pin for the bi-directional, differential RF I/O port.
3.2.14 RFP
RFP is the positive terminal for the bi-directional, differential RF I/O port.
3.2.15 RFN
RFN is the negative terminal for the bi-directional, differential RF I/O port.
3.2.16 RSTN
Reset input. A low level on this pin for longer than the minimum pulse length will
generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to
generate a reset.
3.2.17 XTAL1
Input to the inverting 16MHz crystal oscillator amplifier. In general a crystal between
XTAL1 and XTAL2 provides the 16MHz reference clock of the radio transceiver.
3.2.18 XTAL2
Output of the inverting 16MHz crystal oscillator amplifier.
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