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參數(shù)資料
| 型號(hào)： | SD6830P |
| 廠(chǎng)商： | AUK Corp |
| 英文描述： | 4BIT MICROCONTROLLER |
| 中文描述： | 4位單片機(jī) |
| 文件頁(yè)數(shù)： | 12/34頁(yè) |
| 文件大?。?/td> | 122K |
| 代理商： | SD6830P |
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KSI-W002-000
12
6.11 Watchdog timer (WDT)
The watchdog timer provides the means to return to a reset condition when a system
malfunction occurs and the program enters an infinite loop caused by noise or any
abnormal state.
Also this timer have a function of oscillation stabilization timer. This is a 13-bit counter,
counts the clock which is divided twelve (F
S YS
/12). In the stop mode the oscillation circuit
stops but when a key input is detected (Port D, Port E) oscillation starts. When 12288 clock
cycles have been counted, the program will be executed from reset address (000H). If the
port C data register’ s value does not change from “L” to “H” before the timer counts 98304
clock cycles, a device reset condition is generated.
The oscillator stabilization time : 12/F
S YS
* 2
10
= 1/F
S YS
* 12288 = 27mS (@455KHz)
The time-out period : 12/F
S YS
* 2
13
= 1/F
S YS
* 98304 = 216mS (@455KHz)
Figure 6-4. Function of Watchdog Timer
SD6830
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