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參數(shù)資料
| 型號(hào)： | SD-14623FX-224 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDFP54 |
| 封裝： | 1.500 X 0.780 INCH, 0.210 INCH HEIGHT, CERAMIC, FP-54 |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 150K |
| 代理商： | SD-14623FX-224 |
6
Data Device Corporation
www.ddc-web.com
SD-14620
J-04/03-0
;;
;
100 ns MAX
EM OR EL
150 ns MAX
DATA
VALID
HIGH Z
;;
;;;
DATA
VALID
500 ns max
INHIBIT
FIGURE 2. CONNECTIONS FOR VOLTAGE
TRANSIENT SUPPRESSORS
FIGURE 4. ENABLE TIMING
FIGURE 3. INHIBIT TIMING
RH
RL
115 V
REF.
INPUT
CR1
CR3
CR2
FOR 90 V SYNCHRO INPUTS
90 V
SYNCHRO
INPUT
S1
HYBRID
S3
S2
CR1, CR2, AND CR3 ARE 1.5kE170CA, BIPOLAR TRANSIENT
VOLTAGE SUPRESSORS OR EQUIVALENT.
CR4 IS A 1.5kE200C.
S1
S3
S2
CR4
BIT, (BUILT-IN-TEST)
This output is an active low logic line that will flag an internal fault
condition or LOS (Loss-Of-Signal). The internal fault detector
monitors the internal loop error and, when it exceeds approximate-
ly ±100 LSBs, will set the line to a logic 0. This condition will occur
during a large-step input and will reset to a logic 1 after the con-
verter settles out. (The BIT is filtered with a 500 s delay.) BIT will
set for an overvelocity condition because the converter loop can not
maintain input/output sync. For the “S” option only, this output will
be active low for an LOR (Loss-Of-Reference) fault condition.
NO FALSE 180° HANGUP
The converter is designed to eliminate a “false 180° reading” dur-
ing instantaneous 180° step changes. This condition most often
occurs when the input is “electronically switched” from a Digital-
to-Synchro converter. If the “MSB” (or 180° bit) is “toggled” on
and off, a converter without the “false 180° hangup” feature may
fail to respond. The condition is artificial, as a “real” synchro or
resolver cannot change its output 180° instantaneously. The con-
dition is most often noticed during wraparound verification tests,
simulations, or troubleshooting.
SYNTHESIZED REFERENCE
The synthesized reference section (“S” option) eliminates errors
due to phase shift between the reference and signal inputs.
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage
(e) in the converter. Due to the inductive nature of synchros and
resolvers, their output signals lead the reference input signal (RH
and RL). When an uncompensated reference signal is used to
demodulate the control transformer’s output, quadrature voltages
are not completely eliminated. As shown in FIGURE 1, the con-
verter synthesizes its own internal reference signal based on the
SIN and COS signal inputs. Therefore, the phase of the synthe-
sized (internal) reference is determined by the signal input, result-
ing in reduced quadrature errors. The synthesized reference cir-
cuit also eliminates the 180 degree false error null hang up.
INTERFACING
SOLID-STATE BUFFER PROTECTION - TRANSIENT
VOLTAGE SUPPRESSION
The solid-state signal and reference inputs are true differential
inputs with high AC and DC common rejection, so most applica-
tions will not require units with isolation transformers. Input imped-
ance is maintained with power off. The recurrent AC peak + DC
common-mode voltage should not exceed the values in TABLE 1.
The 90 V line-to-line systems may have voltage transients which
exceed the 300 V specification listed in TABLE 1. These tran-
sients can destroy the thin-film input resistor network in the
hybrid. Therefore, 90 V L-L solid-state input modules may be
protected by installing voltage suppressors (See FIGURE 2).
Voltage transients are likely to occur whenever a synchro is
switched on and off. For instance, a 1000 V transient can be gen-
erated when the primary of a CX or TX input is opened.
INHIBIT AND ENABLE TIMING
The Inhibit (INH) signal is used to freeze the digital output angle
in the transparent output data latch while the data is being trans-
ferred. Application of an inhibit signal does not interfere with the
continuous tracking of the converter. As shown in FIGURE 3,
angular output data is valid 500 nanoseconds (maximum) after
the application of the low-going Inhibit pulse.
Output angle data is enabled onto the tri-state data bus in four
bytes. This Enable MSB (EM-A or EM-B) is used for the most sig-
nificant 8 bits and Enable LSB (EL-A or EL-B) is used for the
least significant bits. As shown in FIGURE 4, output data is valid
150 nanoseconds (maximum) after the application of a low-going
enable pulse. The tri-state data bus returns to the high imped-
ance state 100 nanoseconds (maximum) after the rising edge of
the enable signal.
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