參數(shù)資料
型號(hào)： SD-14597F3-222L
廠商： DATA DEVICE CORP
元件分類： 位置變換器
英文描述： SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDFP36
封裝： CERAMIC, FP-36
文件頁數(shù)： 1/14頁
文件大小： 416K
代理商： SD-14597F3-222L
SD-14595/96/97
SYNCHRO/RESOLVER-TO-DIGITAL
CONVERTERS
DESCRIPTION
The SD-14595 is a low-cost, high
reliability, synchro- or resolver-to-dig-
ital converter with 14-bit-only, 16-bit-
only or pin programmable 14-bit or
16-bit resolution. Packaged in a 36-
pin DDIP, the SD-14595/96/97 series
feature Built-In-Test (BIT) output.
The SD-14595/96/97 series accepts
broadband inputs: 360 to 1 kHz. Other
features are solid-state signal and ref-
erence isolation and high common
mode rejection. In addition, the SD-
14596 and SD-14597 are pin-for-pin
replacements for the Natel 1044 and
1046, respectively.
The digital angle output from the
SD-14595/96/97 is a natural binary
code, parallel positive logic and is
TTL/CMOS
compatible. The
SD-
14595/96/97 accomplishes synchro-
nization to a computer with the
Converter Busy (CB) output and/or the
Inhibit (INH) input.
APPLICATIONS
Because of its high reliability, small
size, and low power consumption, the
SD-14595/96/97 is ideal for military
ground or avionics applications. All
models are available with MIL-PRF-
38534 processing.
Designed with three-state output, the
SD-14595/96/97 is especially well-
suited for use with computer based
systems. Among the many possible
applications are radar and navigation
systems, fire control systems, flight
instrumentation, and flight trainers or
simulators.
FEATURES
Single +5 V Power Supply
Accuracy to 1.3 Arc Minutes
Pin Programmable 14 Bit/16 Bit,
14 Bit Only or 16 Bit Only
No 180° False Lock-up
Internal Synthesized Reference
Built-In-Test (BIT) Output
Low Power
Pin-for-Pin Replacement for
Natel’s 1044 and 1046
HIGH
ACCURACY
CONTROL
TRANSFORMER
GAIN
DEMODULATOR
ERROR
PROCESSOR
VCO
16 BIT
UP/DOWN
COUNTER
U
T
VEL
D
SIN
(
θ-φ)
e
SIN
θ
COS
θ
3 STATE
TTL BUFFER
3 STATE
TTL BUFFER
VOLTAGE
DOUBLER
INHIBIT
TRANSPARENT
LATCH
16 BIT CT
TRANSPARENT
LATCH
16 BIT OUTPUT
TRANSPARENT
LATCH
EDGE
TRIGGERED
LATCH
DIGITAL
ANGLE
φ
Q
+8.6 V
INH
BITS 1-8
HBE
50 ns DELAY
RESOLUTION
CONTROL
1 LSB ANTIJITTER FEEDBACK
LOS
SYNTHESIZED
REF
REFERENCE
CONDITIONER
BIT DETECT
RH
RL
REF IN
LOS
ANALOG RETURN
V(+4.3 V)
V
+5 V
14B
LBE
BITS 9-16
T
U
INH
R
E
CB
VEL
e
BIT
(14595 ONLY)
S1
S2
S3
SOLID STATE SYNCHRO INPUT OPTION
ELECTRONIC
SCOTT T
SIN
θ
COS
θ
S1
S2
S3
SOLID STATE RESOLVER INPUT OPTION
RESOLVER
CONDITIONER
SIN
θ
COS
θ
S4
DIRECT INPUT OPTION
VOLTAGE
FOLLOWER
BUFFER
SIN
θ
COS
θ
SIN
θ
COS
θ
INPUT OPTIONS
V
INTERNAL
DC
REFERENCE
INPUT OPTION
1997, 1999 Data Device Corporation
FIGURE 1. SD-14595/96/97 BLOCK DIAGRAM
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