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參數(shù)資料
| 型號： | 9S12E128DGV1 |
| 廠商： | Motorola, Inc. |
| 英文描述： | MC9S12E-Family Device User Guide V01.04 |
| 中文描述： | MC9S12E -系列設(shè)備的用戶手冊V01.04 |
| 文件頁數(shù)： | 84/156頁 |
| 文件大小： | 3077K |
| 代理商： | 9S12E128DGV1 |
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Device User Guide — 9S12E128DGV1/D V01.04
84
2.3.14 PE1 /
IRQ — Port E input Pin 1 / Maskable Interrupt Pin
PE1 is always an input and can always be read. The PE1 pin is also the IRQ input used for requesting an
asynchronous interrupt to the MCU. During reset, the I bit in the condition code register (CCR) is set and
any IRQ interrupt is masked until software enables it by clearing the I bit. The IRQ is software
programmable to either falling edge-sensitive triggering or level-sensitive triggering based on the setting
of the IRQE bit in the IRQCR register. The IRQ is always enabled and configured to level-sensitive
triggering out of reset. It can be disabled by clearing IRQEN bit in the IRQCR register. There is an active
pull-up on this pin while in reset and immediately out of reset. The pullup can be turned off by clearing
PUPEE in the PUCR register.
2.3.15 PE0 / XIRQ — Port E input Pin 0 / Non Maskable Interrupt Pin
PE0 is always an input and can always be read. The PE0 pin is also the XIRQ input for requesting a
nonmaskable asynchronous interrupt to the MCU. During reset, the X bit in the condition code register
(CCR) is set and any XIRQ interrupt is masked until MCU software enables it by clearing the X bit.
Because the XIRQ input is level sensitive triggered, it can be connected to a multiple-source wired-OR
network. There is an active pull-up on this pin while in reset and immediately out of reset. The pullup can
be turned off by clearing PUPEE in the PUCR register.
2.3.16 PK7 / ECS / ROMCTL — Port K I/O Pin 7
PK7 is a general purpose input or output pin. During MCU expanded modes of operation, when the EMK
bit in the MODE register is set to 1, this pin is used as the emulation chip select output (ECS). In expanded
modes the PK7 pin can be used to determine the reset state of the ROMON bit in the MISC register. At
the rising edge of RESET, the state of the PK7 pin is latched to the ROMON bit. There is an active pull-up
on this pin while in reset and immediately out of reset. The pullup can be turned off by clearing PUPKE
in the PUCR register. Refer to the HCS12 MEBI Block Guide for further details. PK7 is not available in
the 80 pin package version.
2.3.17 PK6 / XCS — Port K I/O Pin 6
PK6 is a general purpose input or output pin. During MCU expanded modes of operation, when the EMK
bit in the MODE register is set to 1, this pin is used as an external chip select signal for most external
accesses that are not selected by ECS. There is an active pull-up on this pin while in reset and immediately
out of reset. The pullup can be turned off by clearing PUPKE in the PUCR register. Refer to the HCS12
MEBI Block Guide for further details. PK6 is not available in the 80 pin package version.
2.3.18 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0]
PK[5:0] are general purpose input or output pins. In MCU expanded modes of operation, when the EMK
bit in the MODE register is set to 1, PK[5:0] provide the expanded address XADDR[19:14] for the external
bus. There are active pull-ups on PK[5:0] pins while in reset and immediately out of reset. The pullup can
be turned off by clearing PUPKE in the PUCR register. Refer to the HCS12 MEBI Block Guide for further
details. PK[5:0] are not available in the 80 pin package version.
F
For More Information On This Product,
Go to: www.freescale.com
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