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參數(shù)資料
| 型號(hào)： | SD-14553FS-855W |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA34 |
| 封裝： | CERAMIC, FP-34 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 115K |
| 代理商： | SD-14553FS-855W |
3
Data Device Corporation
www.ddc-web.com
SD-14550 Series
Rev. H
TABLE 1. SD-14550 SERIES SPECIFICATIONS
These specs apply over the rated power supply, temperature, and refer-
ence frequency ranges; 10% signal amplitude variation, and 10% har-
monic distortion.
PARAMETER
UNIT
VALUE
RESOLUTION
Bits
programmable 10, 12, 14, or 16
ACCURACY
Min
1, 2 or 4, + 1 LSB (see TABLE 4)
REPEATABILITY
LSB
1 max.
DIFFERENTIAL LINEARITY
LSB
(RH, RL)
differential
2 & 11.8 V UNITS
90 V UNIT
1 max.
REFERENCE INPUT
Type
SD-14550
Voltage Range
Frequency
Input Impedance
single ended
differential
Common-Mode Range
SD-14550XS
Voltage Range
Frequency
Input Impedance
single ended
differential
Common-Mode Range
±Sig/Ref Phase Shift
Vrms
Hz
Ohm
Vpeak
Vrms
Hz
Ohm
Vpeak
deg.
2-35
360 - 5K
60K
120K
50,
100 transient
2-35
1K - 5K
40K
80K
50,
100 transient
45 max.
10-130
60 (47-5K)
400 (360-5K)
270K min.
540K min.
200,
300 transient
—
SIGNAL INPUT
CHARACTERISTICS
90 V Synchro Input (L-L)
Zin line-to-line
Zin line-to-ground
Common-Mode Voltage
11.8 V Synchro Input (L-L)
Zin line-to-line
Zin line-to-ground
Common-Mode Voltage
11.8 V Resolver Input (L-L)
Zin line-to-line
Zin line-to-ground
Common-Mode Voltage
2 V Direct Input (L-L)
Voltage Range
Max. Voltage w/o Damage
Input Impedance
2 V Resolver Input (L-L)
Zin line-to-line
Zin line-to-ground
Common-Mode Voltage
Ohm
V
Ohm
V
Ohm
V
Vrms
V
Ohm
V
123K
80K
180 max.
52K
34K
30 max.
(same for “S” option)
140K
70K
30 max.
2 nom, 2.3 max.
25 cont, 100 pk transient
20 M || 10 pF min.
(“S” option only)
11K
22K
4.9 max.
TABLE 1. SD-14550 SERIES SPECS. (CONTINUED)
PARAMETER
UNIT
VALUE
DIGITAL INPUT/OUTPUT
INPUTS (CONTINUED)
Inhibit (lNH)
Enable Bits 1 to 8 (EM)
Enable Bits 9 to 16 (EL)
OUTPUTS
Parallel Data
Built-In-Test
Drive Capability
bits
TTL
CMOS
Logic 0 inhibits; Data
stable within 0.5 s
Logic 0 enables; Data stable
within 150 ns
Logic 1 = High Impedance
Data High Z within 100 ns
16 parallel lines; 2 bytes
natural binary angle, posi-
tive logic.
LOGIC 0 = BIT condition.
~ ± 100 LSBs of error with
a filter of 500 s for LOS.
(LOS and LOR for “S” option)
50 PF +
Logic 0; 1 TTL load, 1.6 mA
at 0.4 V max
Logic 1; 10 TTL loads,
-0.4 mA at 2.8 V min
Logic 0; 100mV max. driving
Logic 1; +5 V supply minus
100 mV min.
VELOCITY CHARACTERISTICS
(see Note 1.)
Polarity
Voltage Range (Full Scale)
Scale Factor
Scale Factor TC
Reversal Error
Linearity
Zero Offset
Zero Offset TC
Load
Noise
±V
±%
ppm/°C
±%
mV
V/°C
KOhm
(Vp/V)%
Positive for increasing angle
4.0 typ.
3.5 min.
10 typ.
20 max.
100 typ.
200 max.
1 typ.
2 max.
0.5 typ.
1 max.
5 typ.
10 max.
15 typ.
30 max.
20 max.
1 typ.
2 max.
POWER SUPPLIES
Nominal Voltage
Voltage Tolerance
Max. Voltage w/o Damage
Current
“S” option
V
%
V
mA
+5
±5
+7
30 typ.
35 max.
30 typ.
35 max.
TEMPERATURE RANGE
Operating
-30X
-20X
-10X
Storage
°C
0 to +70
-40 to +85
-55 to +125
-65 to +150
PHYSICAL
CHARACTERISTICS
Size
Weight
1.00 x 0.78 x 0.21
(25.4 x 19.81 x 5.33)
0.44
(12.47)
in
(mm)
oz
(g)
DIGITAL INPUT/OUTPUT
LOGIC TYPE
INPUTS
Resolution Control
TTL/CMOS compatible
Logic 0 = 0.8 V max.
Logic 1 = 2.0 V min.
Loading =10 A max P.U. current
source to +5 V || 5 pF max.
CMOS transient protected.
See TABLE 2.
NOTES:
1. Refer to TABLE 3 for full-scale tracking rate.
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