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參數(shù)資料
| 型號： | SD-14531F5-475S |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
| 封裝： | CERAMIC, FP-36 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 170K |
| 代理商： | SD-14531F5-475S |
10
Data Device Corporation
www.ddc-web.com
SD-14531
TABLE 4. VELOCITY CHARACTERISTICS
PARAMETER
UNITS
TYP
MAX
Polarity
VEL is negative for positive angular rate.
Device Type
Output Voltage (see note)
V
400 Hz
60 Hz
1.1
400 Hz
60 Hz
1.1
Voltage Scaling
rps/1.1 V See Vel. Voltage Scaling TABLE 5.
Scale Factor Error
Reversal Error
Linearity Error
Zero Offset
Load
%
% output
mV
mA
10
1
0.5
5
0.5
10
1
0.5
5
0.5
15
2
1
20
0.5
15
2
1
20
0.5
Note: With respect to Analog Return (V)
TABLE 5. VELOCITY VOLTAGE SCALING
(values in V/rps)
14 BIT
DEVICE TYPE
16 BIT
0.11
0.56
400 Hz
60 Hz
0.44
2.23
Note: If the resolution is changed while the input is changing, then
the velocity output voltage and the digital output will have a transient
until it settles to the new velocity scaling at a speed determined by
the bandwidth.
SD-14531
16 BIT BUS
(MSB) BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
BIT 14
BIT 15
(LSB) BIT 16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HBE
LBE
INH
DATA 1-16
VALID
500 ns MIN
150 ns MIN
100 ns MAX
HBE, LBE
FIGURE 14. 16-BIT DATA TRANSFER TIMING
FIGURE 13. 16-BIT DATA TRANSFER
and accuracy are dependent solely on the linearity and accura-
cy of the VCO.
The VEL output can swing ±1.10 V with respect to Analog Return
(V). The analog output VEL characteristics are listed in TABLES
4 and 5.
The VEL output has DC tachometer quality specs such that it
can be used as the velocity feedback in servo applications.
INTERFACING - DYNAMIC PERFORMANCE
A Type II servo loop (KV =
∞) and very high acceleration con-
stants give the SD-14531 superior dynamic performance. If the
power supply voltage is not the +5 V DC nominal value, the spec-
ified input rates will increase or decrease in proportion to the
fractional change in voltage.
TRANSFER FUNCTIONS
The dynamic performance of the converter can be determined
from its transfer function block diagram (FIGURE 15) and open
and closed loop Bode plots (FIGURES 16 and 17). Values for the
transfer function block can be obtained from TABLE 6.
RESPONSE PARAMETERS
As long as the converter’s maximum tracking rate is not exceed-
ed, there will be no velocity lag in the converter output although
momentary acceleration errors remain. If a step input occurs, as
when the power is initially applied, the response will be critically
damped. FIGURE 18 shows the response to a step input. After
initial slewing at the maximum tracking rate of the converter,
there is one overshoot (which is inherent in a Type II servo). The
overshoot settling to a final value is a function of the small signal
settling time.
FASTER SETTLING TIME USING “BIT” TO REDUCE
RESOLUTION
Since the SD-14531 has higher precision in the 16-bit mode and
faster settling in the 14-bit mode, the BIT output can be used to
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| SD-14531F5-475Z | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
| SD-14531F5-354S | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
| SD-14531F5-354W | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
| SD-14531F5-354Y | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
| SD-14531F5-354Z | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
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