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參數(shù)資料
| 型號： | SD-14531F5-382W |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
| 封裝： | CERAMIC, FP-36 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 170K |
| 代理商： | SD-14531F5-382W |
8
Data Device Corporation
www.ddc-web.com
SD-14531
;
DEPENDS ON d
φ/dt
0.8-3.0
s
CB
0.2
s
DATA
VALID
6.1
s MIN
;;
;
0.5 s
INH
100 ns MIN
DATA
UPDATE
STABLE
1 s MIN
;;
DATA
VALID
0.5
s
ASYNCHROUS TO CB
INH
;;;;
100 ns MAX
HBE OR LBE
150 ns MIN
OUTPUT
VALID
HIGH Z
FIGURE 8. CONVERTER BUSY TIMING DIAGRAM
FIGURE 7. TRI-STATE OUTPUT TIMING
FIGURE 10. OUTPUT DATA UPDATE TIMING
FIGURE 9. INHIBIT TIMING DIAGRAM
TABLE 3. DIGITAL ANGLE OUTPUTS
BIT
DEG/BIT
MIN/BIT
1(MSB ALL MODES)
2
3
4
5
6
7
8
9
10
11
12
13
14(LSB 14 BIT MODE)
15
16(LSB 16 BIT MODE)
180
90
45
22.5
11.25
5.625
2.813
1.405
0.7031
0.3516
0.1758
0.0879
0.0439
0.0220
0.0110
0.0055
10800
5400
2700
1350
675
337.5
168.75
84.38
42.19
21.09
10.55
5.27
2.64
1.32
0.66
0.33
Note: HBE enables the 8 MSBs and LBE enables the LSBs.
3. As HBE is set to a high state (logic 1), LBE is brought low for
a 150 ns MIN before the LSB data is valid and transferred.
4. LBE should go high (to logic 1) at least 100 ns MAX before
another device uses the bus.
5. INH goes high and data transfer is done and the data refresh
cycle can begin. Note the time it takes for INH to go to a logic 1
should be 100 ns minimum before valid data is transferred.
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