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參數(shù)資料
| 型號： | SD-14531F3-885W |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
| 封裝： | CERAMIC, FP-36 |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 170K |
| 代理商： | SD-14531F3-885W |
9
Data Device Corporation
www.ddc-web.com
SD-14531
SD-14531
8 BIT BUS
(MSB) BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
BIT 14
BIT 15
(LSB) BIT 16
D7
D6
D5
D4
D3
D2
D1
D0
HBE
LBE
INH
DATA 1-8
VALID
DATA 9-16
VALID
500 ns MIN
150 ns MIN
100 ns MAX
150 ns MIN
100 ns MAX
LBE
HBE
FIGURE 11. 8-BIT DATA TRANSFER
FIGURE 12. 8-BIT DATA TRANSFER TIMING
Note: For further understanding refer to the beginning of this sec-
tion (i.e., Digital Interface, Digital Angle Outputs, Digital Angle
Output Timing, and Inhibit).
DATA TRANSFER TO 16-BIT BUS
Data transfer to the 16-bit bus is much simpler than the 8-bit bus.
FIGURES 13 and 14 show the connections and timing for trans-
ferring data from the SD-14531 to a 16-bit bus.
As can be seen by the timing diagram the following occurs:
1. The converter INH control is applied and must remain low for
a minimum of 500 ns before valid data is transferred.
2. HBE and LBE are set to a low state (logic 0) 350 ns minimum
after INH goes low and must remain low for a minimum of 150 ns
before the data (1-16) is valid and transferred.
3. HBE and LBE should go high (to logic 1) at least 100 ns MAX
before another device uses the bus.
4. INH goes high and data transfer is done and the data refresh
cycle can begin. Note the time it takes for INH to go to a logic 1
should be 100 ns minimum before valid data is transferred.
Note: For further understanding refer to the beginning of this sec-
tion (i.e., Digital Interface, Digital Angle Outputs, Digital Angle
Output Timing, and Inhibit).
INTERFACING - ANALOG OUTPUTS
The analog outputs are AC error (e), Analog Return (V), and
Velocity (VEL).
AC ERROR (e, PIN 12)
The AC error is proportional to the difference between the input
angle
θ and the digital input angle φ, (θ-φ), with a scaling of:
3.5 mV rms/LSB (14-bit mode)
1.75 mV rms/LSB (16-bit mode)
The e output can swing ±3 V min with respect to Analog Return (V).
ANALOG RETURN (V, PIN 11)
This internal voltage is not required externally for normal opera-
tion of the converter. It is used as the internal DC reference and
the return for the VEL and e outputs. It is nominally +4.3 V and is
proportional to the +5 V DC supply.
VELOCITY (VEL, PIN 10)
The velocity output (VEL, pin 10) is a DC voltage proportional to
angular velocity d
θ/dt. The velocity is the input to the voltage-
controlled oscillator (VCO), as shown in FIGURE 1. Its linearity
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| SD-14531F3-885Y | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
| SD-14531F3-885Z | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
| SD-14531F3-892W | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
| SD-14531F3-892Y | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
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