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參數(shù)資料
| 型號： | SD-14531F2-155Q |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDMA36 |
| 封裝： | CERAMIC, FP-36 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 170K |
| 代理商： | SD-14531F2-155Q |
5
Data Device Corporation
www.ddc-web.com
SD-14531
and reset after the converter settles out. BIT will also change to logic
1 for an over-velocity condition, because the converter loop cannot
maintain input-output and/or if the converter malfunctions where it
cannot maintain the loop at a null. BIT will also be set for a Loss-of-
Signal (LOS) and/or a Loss-of-Reference (LOR).
PROGRAMMABLE RESOLUTION (14B, PIN 16)
Resolution is controlled by one logic input,14B. The resolution
can be changed during converter operation so the appropriate
resolution and velocity dynamics can be changed as needed. To
insure that a race condition does not exist between counting and
changing the resolution, input 14B is latched internally on the
trailing edge of CB (see FIGURE 2).
INTERFACING - INPUTS
SIGNAL INPUT OPTIONS
The SD-14531 series offers programmable synchro or resolver
inputs. In a synchro or resolver, shaft angle data is transmitted as
the ratio of carrier amplitudes across the input terminals.
Synchro signals, which are of the form sin
θcosωt, sin(θ+120°)
(e) in the converter. A digital position error will result due to the
interaction of this quadrature voltage and a reference phase shift
between the converter signal and reference inputs. The magni-
tude of this error is given by the following formula:
Magnitude of Error=(Quadrature Voltage/F.S.signal) tan(
α)
Where:
Magnitude of Error is in radians,
Quadrature Voltage is in volts,
Full Scale signal is in volts,
α = signal-to-REF phase shift.
An example of the magnitude of error is as follows:
Let:
Quadrature Voltage = 11.8 mV
Let:
F.S. signal = 11.8 V
Let:
α = 6°
Then: Magnitude of Error = 0.35 min
1 LSB in the 16th bit.
Note: Quadrature is composed of static quadrature which is
specified by the synchro or resolver supplier plus the speed volt-
age which is determined by the following formula:
Speed Voltage=(rotational speed/carrier frequency) F.S. signal
Where:
Speed Voltage is the quadrature due to rotation,
Rotational speed is the rps (rotations per second) of the
synchro or resolver,
Carrier frequency is the REF in Hz.
BUILT-IN-TEST (BIT, PIN 15)
The Built-In-Test output (BIT) monitors the level of error (D) from the
demodulator. D represents the difference in the input and output
angles and ideally should be zero; if it exceeds approximately 180
LSBs (of the selected resolution) the logic level at BIT will change
from a logic 0 to logic 1. This condition will occur during a large step
;;;
;;
14B
0
s MIN
CB
0.1
s MIN
30
90
150
210
270
330
360
θ
(DEGREES)
CCW
In
Phase
with
RL-RH
of
Converter
and
R2-R1
of
CX.
0
S1-S3 = V
SIN
θ
MAX
S3-S2 = V
SIN(
θ + 120°)
MAX
S2-S1 = V
SIN(
θ + 240°)
MAX
- V
MAX
+ V
MAX
30
90
150
210
270
330
360
θ
(DEGREES)
CW
In
Phase
with
RH-RL
of
Converter
and
R2-R4
of
RX.
0
S2-S4 = V
COS
θ
MAX
S3-S1 = V
SIN(
θ)
MAX
- V
MAX
+ V
MAX
FIGURE 2. RESOLUTION CONTROL TIMING DIAGRAM
Standard Resolver Control Transmitter (RX) Outputs as a Function of CW Rotation
From Electrical Zero (EZ) With R2-R4 Excited.
Standard Synchro Control Transmitter (CX) Outputs as a Function of CCW Rotation
From Electrical Zero (EZ).
FIGURE 3. SYNCHRO AND RESOLVER SIGNALS
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