參數(shù)資料
型號: SCN2652AC2F40
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: HEATSINK TO-220 W/SHURLOCK-CLIP
中文描述: 1 CHANNEL(S), 2M bps, MULTI PROTOCOL CONTROLLER, CDIP40
封裝: CERAMIC, DIP-40
文件頁數(shù): 17/28頁
文件大?。?/td> 651K
代理商: SCN2652AC2F40
Philips Semiconductors
Product specification
SCN2652/SCN68652
Multi-protocol communications controller (MPCC)
1995 May 01
17
AC ELECTRICAL CHARACTERISTICS
1, 2, 3
PARAMETER
2MHz CLOCK
Typ
UNIT
Min
Max
Set-up and hold time
t
ACS
Address/control set-up
t
ACH
Address/control hold
t
DS
Data bus set-up (write)
t
DH
Data bus hold (write)
t
RXS
Receiver serial data set-up
t
RxH
Receiver serial data hold
Pulse width
t
RES
RESET
t
DBEN
DBEN
Delay Time
t
DD
Data bus (read)
t
TxD
Transmit serial data
t
DBEND
DBEN to DBEN delay
t
DF
Data bus float time (read)
f
Clock (RxC, TxC) frequency
50
0
50
0
150
150
ns
250
250
ns
m
4
170
250
ns
200
150
ns
2.0
MHz
t
CLK1
t
CLK2
t
CLK0
Clock high (MM = 0)
Clock high (MM = 1)
Clock low
165
240
240
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature
range and operating supply range.
2. All voltage measurements are referenced to ground. All time measurements are at 0.8V or 2.0V. Input voltage levels for testing are 0.4V and
2.4V.
3. Output load C
= 100pF.
4. m = TxC low and applies to writing to TDSR
H
only.
TIMING DIAGRAMS
RESET
t
RES
RESET
RESET AND WRITE DATA BUS
t
DBEN
t
ACS
DBEN
A
0
,
A
2
t
ACH
t
ACS
t
ACH
CE, R/W,
BYTE
t
DF
t
DD
FLOATING
VALID
VALID
FLOATING
NOT
D
0
–D
15
(READ)
t
DS
t
DH
D
0
–D
15
(WRITE)
SD00065
Figure 10. Timing Diagrams
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