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參數(shù)資料
| 型號： | SCM6341ZP15A |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 128K x 24 Bit Static Random Access Memory |
| 中文描述： | 128K X 24 STANDARD SRAM, 15 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 124K |
| 代理商： | SCM6341ZP15A |
MCM6341
7
MOTOROLA FAST SRAM
WRITE CYCLE 1
(W Controlled; See Notes 1, 2, 3, and 4)
Parameter
Symbol
b l
MCM6341–10
MCM6341–11
MCM6341–12
MCM6341–15
U i
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time
tAVAV
tAVWL
tAVWH
tAVWH
10
—
11
—
12
—
15
—
ns
5
Address Setup Time
0
—
0
—
0
—
0
—
ns
Address Valid to End of Write
9
—
10
—
10
—
12
—
ns
Address Valid to End of Write (G
High)
8
—
9
—
9
—
10
—
ns
Write Pulse Width
tWLWH
tWLEH
9
—
10
—
10
—
12
—
ns
Write Pulse Width (G High)
tWLWH
tWLEH
8
—
9
—
9
—
10
—
ns
Data Valid to End of Write
tDVWH
tWHDX
tWLQZ
tWHQX
tWHAX
4
—
5
—
5
—
6
—
ns
Data Hold Time
0
—
0
—
0
—
0
—
ns
Write Low to Data High–Z
0
5
0
6
0
6
0
7
ns
6, 7, 8
Write High to Output Active
3
—
3
—
3
—
3
—
ns
6, 7, 8
Write Recovery Time
0
—
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
5. All write cycle timings are referenced from the last valid address to the first transitioning address.
6. Transition is measured
±
200 mV from steady–state voltage.
7. This parameter is sampled and not 100% tested.
8. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.
DATA VALID
HIGH–Z
HIGH–Z
tAVAV
tAVWH
tWHAX
tWHDX
tWHQX
tWLWH
tWLEH
tAVWL
tDVWH
tWLQZ
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
WRITE CYCLE 1
(W Controlled; See Notes 1, 2, 3, and 4)
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