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參數(shù)資料
| 型號： | SCM6323AYJ12A |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 64K x 16 Bit 3.3 V Asynchronous Fast Static RAM |
| 中文描述： | 64K X 16 STANDARD SRAM, 12 ns, PDSO44 |
| 封裝： | 0.400 INCH, SOJ-44 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 181K |
| 代理商： | SCM6323AYJ12A |
MCM6323A
8
MOTOROLA FAST SRAM
WRITE CYCLE 2
(E Controlled, See Notes 1 and 2)
Parameter
Symbol
b l
MCM6323A–10
MCM6323A–12
MCM6323A–15
U i
Unit
Notes
Min
Max
Min
Max
Min
Max
Write Cycle Time
tAVAV
tAVEL
tAVEH
tELEH,
tELWH
10
—
12
—
15
—
ns
3
Address Setup Time
0
—
0
—
0
—
ns
Address Valid to End of Write
8
—
9
—
10
—
ns
Enable to End of Write
8
—
9
—
10
—
ns
4, 5
Data Valid to End of Write
tDVEH
tEHDX
tEHAX
4
—
5
—
6
—
ns
Data Hold Time
0
—
0
—
0
—
ns
Write Recovery Time
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low, W low, and LB and/or UB low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.
5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2
(E Controlled)
tEHDX
tDVEH
tEHAX
tELWH
tELEH
tAVEL
tAVEH
DATA VALID
tAVAV
HIGH–Z
A (ADDRESS)
W (WRITE ENABLE)
E (CHIP ENABLE)
Q (DATA OUT)
D (DATA IN)
LB, UB (BYTE ENABLE)
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| SCM6323AYJ12AR | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 16 Bit 3.3 V Asynchronous Fast Static RAM |
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