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參數(shù)資料
| 型號： | SCF5744 |
| 廠商： | SIEMENS A G |
| 元件分類： | 顯示用LED |
| 英文描述： | 0.270” 4-Character, 5x7 Dot Matrix Serial Input Dot Addressable Intelligent Display |
| 中文描述： | 5X7 DOT MATRIX DISPLAY, HIGH EFFICIENCY GREEN, 6.86 mm |
| 封裝： | PLASTIC, DIP-22 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 93K |
| 代理商： | SCF5744 |
2–210
SCF5740/2/4
Figure 11. Display Interface to Siemens/Intel 8031 Microprocessor (using one bit of parallel port as serial port)
Figure 12. Display Interface with Motoroal 68HC05C4 Microprocessor (using SPI Port)
Figure 13. Cascading Multiple Displays
Multiple displays can be cascaded using the CLK SEL and CLK I/O pins (Figure 13). The display designated as the Master-
Clock source should have its CLK SEL pin tied high and the slaves should have their CLK SEL pins tied low. All CLK I/O pins
should be tied together. One display CLK I/O can drive 15 slave CLK I/Os. Use RST to synchronize all display counters.
V
CC
V
CC
U1
8031
1
9
20
RST
P1.0
18
19
XTAL2
XTAL1
40 P3.0
P3.1
P3.6
P0.0
10
11
16
39
V
CC
10
21
8
22
μ
F
TAN
+
.01
μ
F
GND
DATA
V
CC
CLKSEL
CLK I/O
SDCLK
LD
RST
GND
ID
15
13
19
2
14
V
CC
V
CC
U1
68HC05C4
1
9
20
RST
PA2
38
39
OSC1
OSC2
40
PA0
PA1
SCLK
MOSI
11
10
33
32
V
CC
10
21
8
22
μ
F
TAN
+
.01
μ
F
GND
DATA
V
CC
CS
CLK I/O
SDCLK
LD
RST
GND
ID
15
13
19
2
14
RST CLK I/O CLK SEL
Intelligent Display
DATA SDCLK
LOAD
14 more displays
in between
RST CLK I/O CLK SEL
Intelligent Display
DATA SDCLK
LOAD
Chip
Address
Decoder
0
15
Address Decode 1–14
V
CC
RST
DATA
SDCLK
A0
A1
A2
A3
LD
CE
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