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參數(shù)資料
| 型號： | SCE5785 |
| 廠商： | SIEMENS A G |
| 元件分類： | 顯示用LED |
| 英文描述： | 5X7 DOT MATRIX DISPLAY, SOFT ORANGE, 4.57 mm |
| 封裝： | PLASTIC, DIP-26 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 295K |
| 代理商： | SCE5785 |
2–193
SCE5780/1/2/3/4/5
The following explains how to format the serial data to be
loaded into the display. The user supplies a string of bit
mapped decoded characters. The contents of this string is
shown in Figure 7a. Figure 7b shows that each character
consist of eight 8 bit words. The rst word encodes the dis-
play character location and the succeeding seven bytes are
row data. The row data represents the status (On, Off) of indi-
vidual column LEDs. Figure 7c shows that each 8 bit word is
formatted to represent Character Address, or Column Data.
Figure 7d shows the sequence for loading the bytes of data.
Bringing the LOAD line low enables the serial register to
accept data. The shift action occurs on the low to high transi-
tion of the serial data clock (SDCLK). The least signicant bit
(D0) is loaded rst. After eight clock pulses the LOAD line is
brought high. With this transition the OPCODE is decoded.
The decoded OPCODE directs D4–D0 to be latched in the
Character Address register, stored in the RAM as Column
data, or latched in the Control Word register. The control IC
requires a minimum 600 ns delay between successive byte
loads. As indicated in Figure 7a, a total of 512 bits of data
are required to load all eight characters into the display.
The Character Address Register selects the character
address that the row and column data will be written to. See
Table 2 for opcode and character addressing. After loading
the Character Address Register, the next seven bytes load
the column data, one row at a time, starting with row 0 (top
row) and ending with row 6 (bottom row). Each character
address has a 7 x 5 bit User RAM formatted as seven rows,
each containing ve column data bits. The three most signi-
cant bits, D7–D5 represent the opcode for the row data and
the least signicant ve bits, D4–D0 represent the column
data. See Table 3 for the column data format. If an address is
loaded before all seven rows are written, the next column
data will be loaded into Row 0 of the new address. The
remaining rows of the old address are not changed.
Table 7 shows the Row Address for the example character,
“D.” Column data is written and read asynchronously from
the 280 bit RAM. Once loaded, the internal oscillator and
character multiplexer reads the data from the RAM. These
characters are row strobed with column data as shown in
Figures 8 and 9. The character strobe rate is determined by
the internal or user supplied external MUX Clock and the
ICs
÷ 320 counter.
Table 7. Character “D”
Op code
D7D6 D5
Column Data
D4 D3 D2 D1 D0
C0 C1 C2 C3 C4
Hex
Row 0
0 0 0
1
0
1E
Row 1
0 0 0
1
0
1
11
Row 2
0 0 0
1
0
1
11
Row 3
0 0 0
1
0
1
11
Row 4
0 0 0
1
0
1
11
Row 5
0 0 0
1
0
1
11
Row 6
0 0 0
1
0
1E
Figure 7a–d. Loading Serial Character Data
Character 0
Character 1
Character 2
Character 3
Character 4
Character 5
Character 6
Character 7
704Clock Cycles, 140.8
s
Time between LOADS
LOAD
Serial
Clock
DATA
Clock
Period
t 0
D0
D1
D2
D3
D4
D5
D6
D7
11 Clock Cycles, 2.2
s
Time
Between
Loads
600ns(min)
OPCODE
Character Address
OPCODE
Column Data
D7
0
D6
0
D5
0
D4
D
D3
D
Time
Between
Loads
600ns(min)
11 Clock Cycles, 2.2
s
Character 0
Address
Row 0 Column
Data
88 Clock Cycles, 17.6
s
Row 1 Column
Data
Row 2 Column
Data
Row 3 Column
Data
Row 4 Column
Data
D7
1
D6
0
D5
1
D4
0
D3
0
D2
0
D1
0
D0
0
a.
b.
c.
d.
Row 5 Column
Data
Row 6 Column
Data
D2
D
D1
D
D0
D
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