參數(shù)資料
型號: SCD5581A
廠商: INFINEON TECHNOLOGIES AG
英文描述: 8-Character 5 x 5 Dot Matrix Serial Input Dot Addressable Intelligent Display
中文描述: 8個字符的5 × 5點陣串行輸入點可尋址智能顯示
文件頁數(shù): 7/15頁
文件大?。?/td> 437K
代理商: SCD5581A
2000 In
fi
neon Technologies Corp.
Optoelectronics Division
San Jose, CA
www.in
fi
neon.com/opto
1-888-In
fi
neon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG
Regensburg, Germany
www.osram-os.com
+49-941-202-7178
SCD5580/1/2/3/4 A
7
March 23, 2000-18
The following explains how to format the serial data to be
loaded into the display. The user supplies a string of bit mapped
decoded characters. The contents of this string is shown in Fig-
ure 8a. Figure 8b shows that each character consist of six 8 bit
words. The first word encodes the display character location
and the succeeding five bytes are row data. The row data rep-
resents the status (On, Off) of individual column LEDs. Figure
9c shows that each that each 8 bit word is formatted to include
a three bit Operational Code (OPCODE) defined by bits D7–D5
and five bits (D4–D0) representing Column Data, Character
Address, or Control Word Data.
Figure 8d shows the sequence for loading the bytes of data.
Bringing the LOAD line low enables the serial register to accept
data. The shift action occurs on the low to high transition of the
serial data clock (SDCLK). The least significant bit (D0) is loaded
first. After eight clock pulses the LOAD line is brought high.
With this transition the OPCODE is decoded. The decoded
OPCODE directs D4–D0 to be latched in the Character Address
register, stored in the RAM as Column data, or latched in the
Control Word register. The control IC requires a minimum 600
ns delay between successive byte loads. As indicated in Figure
8a, a total of 528 bits of data are required to load all eight char-
acters into the display.
Figure 8. Loading Serial Character Data
Character 0
Character 1
Character 2
Character 3
Character 4
Character 5
Character 6
Character 7
528 Clock Cycles, 105.6
μ
s
Example: Serial Clock = 5 MHz, Clock Period = 200 ns
Time between LOADS
LOAD
Serial
Clock
DATA
Clock
Period
t0
D0
D1
D2
D3
D4
D5
D6
D7
11 Clock Cycles, 2.2
μ
s
Time
Between
Loads
600 ns(min.)
OPCODE
D5
1
0
Character Address
D0
0
0
0
OPCODE
Column Data
D1
C3
C2
D0
C4
D2
D3
C1
D4
C0
Character 0
Address
Row 0 Column
Data
66 Clock Cycles, 13.2
μ
s
Row 1 Column
Data
Row 2 Column
Data
Row 3 Column
Data
Row 4 Column
Data
D1
D2
D3
0
D4
0
D6
D7
1
D5 D6 D7
a.
b.
c.
d.
11 Clock Cycles, 2.2
μ
s
Time
Between
Loads
600 ns(min.)
D5
The Character Address Register bits, D4–D0 (Table 2), and Row
Address Register bits, D7–D5 (Table 3), direct the Column Data
bits, D4–D0 (Table 3) to specific RAM location. Table 1 shows
the Row Address for the example character “D.” Column data
is written and read asynchronously from the 200 bit RAM.
Once loaded the internal oscillator and character multiplexer
reads the data from the RAM. These characters are row
strobed with column data as shown in Figures 10 and 11. The
character strobe rate is determined by the internal or user sup-
plied external MUX Clock and the IC’s ÷320 counter.
Table 1. Character
D
Op code
D7 D6 D5
Column Data
D4 D3 D2 D1 D0
C0 C1 C2 C3 C4
Hex
Row 0
0
0
0
1
1
1
1
0
1E
Row 1
0
0
1
1
0
0
0
1
31
Row 2
0
1
0
1
0
0
0
1
51
Row 3
0
1
1
1
0
0
0
1
71
Row 4
1
0
0
1
1
1
1
0
9E
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