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參數(shù)資料
| 型號： | SCD223110QCD |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 256K bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | METRIC, QFP-100 |
| 文件頁數(shù)： | 1/178頁 |
| 文件大?。?/td> | 2247K |
| 代理商： | SCD223110QCD |
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CD2231
Intelligent Two-Channel LAN and WAN Communications Controller
Datasheet
The CD2231 is a two-channel multi-protocol synchronous/asynchronous communications
controller specifically designed to reduce host-system processing overhead and increase
efficiency in a wide variety of communications applications. The CD2231 is packaged in a 100-
pin MQFP, and offers eight clock/modem pins per channel. The device has two fully
independent serial channels that support asynchronous, asynchronous-HDLC (PPP),
synchronous HDLC/SDLC, SLIP, and MNP 4 protocols at serial data rates up to 256 kbps,
(230.4 kbps in async modes) when clocked by a 35-MHz source.
The device is based on a proprietary on-chip RISC processor that performs all time-critical, low-
level tasks that are otherwise performed by the host system.
The CD2231 boosts system efficiency with on-chip DMA, on-chip FIFOs, intelligent vectored
interrupts, and intelligent protocol processing. The on-chip DMA controller provides ‘fire-and-
forget’ transmit support — the host need only inform the CCD2231 of the location of the packet
to be sent. Similarly, on receive, the CD2231 automatically receives a complete packet with no
host intervention or assistance required. The DMA controller also has an ‘Append mode’ for use
in asynchronous applications.
The DMA controller uses a dual-buffer scheme that easily implements simple or complex buffer
schemes. Each channel and direction has two active buffers.
The CD2231 can be programmed to interrupt the host at the completion of a frame or buffer. In
applications where buffers are of a small, fixed size, the dual-buffer scheme allows large frames
to be divided into multiple buffers.
For applications where a DMA interface is not desired, the device can be operated as an
interrupt-driven or polled device. This choice is available individually for each channel and each
direction. For example, a channel can be programmed for DMA transmit and interrupt-driven
receive.
In either case, 16-byte FIFOs on each channel and in each direction reduce latency time
requirements, making both software and hardware designs less time-critical. Threshold levels on
FIFOs are user-programmable.
Efficient vectored interrupts are another way the CD2231 helps system efficiency. Separate
interrupts are generated for transmit, receive, and modem-signal change with unique user-
defined vectors for each type and channel. This allows very flexible interfacing and fast,
efficient interrupt coding.
As of May 2001, this document replaces the Basis
Communications Corp. document
May 2001
CL-CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller.
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