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參數(shù)資料
| 型號(hào)： | SCC68681C1A44,529 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 7/29頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC UART DUAL 44-PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Stand-Alone UARTs |
| 標(biāo)準(zhǔn)包裝： | 26 |
| 特點(diǎn)： | 故障啟動(dòng)位檢測(cè) |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 3 位 |
| 電源電壓： | 5V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC |
| 包裝： | 管件 |
| 其它名稱： | 568-3527-5 935274497529 SCC68681C1A44-S |
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Philips Semiconductors
Product data
SCC68681
Dual asynchronous receiver/transmitter (DUART)
2004 Apr 06
15
OPCR – Output Port Configuration Register
OPCR[7] – OP7 Output Select
This bit programs the OP7 output to provide one of the following:
0: The complement of OPR[7].
1: The Channel B transmitter interrupt output which is the comple-
ment of TxRDYB. When in this mode OP7 acts as an open-
drain output. Note that this output is not masked by the contents
of the IMR.
OPCR[6] – OP6 Output Select
This bit programs the OP6 output to provide one of the following:
0: The complement of OPR[6].
1: The Channel A transmitter interrupt output which is the comple-
ment of TxRDYA. When in this mode OP6 acts as an open-
drain output. Note that this output is not masked by the contents
of the IMR.
OPCR[5] – OP5 Output Select
This bit programs the OP5 output to provide one of the following:
0: The complement of OPR[5].
1: The Channel B transmitter interrupt output which is the comple-
ment of ISR[5]. When in this mode OP5 acts as an open-drain
output. Note that this output is not masked by the contents of
the IMR.
OPCR[4] – OP4 Output Select
This field programs the OP4 output to provide one of the following:
0: The complement of OPR[4].
1: The Channel A receiver interrupt output which is the comple-
ment of ISR[1]. When in this mode OP4 acts as an open-drain
output. Note that this output is not masked by the contents of
the IMR.
OPCR[3:2] – OP3 Output Select
This bit programs the OP3 output to provide one of the following:
00: The complement of OPR[3].
01: The counter/timer output, in which case OP3 acts as an open-
drain output. In the timer mode, this output is a square wave at
the programmed frequency. In the counter mode, the output
remains HIGH until terminal count is reached, at which time it
goes LOW. The output returns to the HIGH state when the
counter is stopped by a stop counter command. Note that this
output is not masked by the contents of the IMR.
10: The 1
× clock for the Channel B transmitter, which is the clock
that shifts the transmitted data. If data is not being transmitted,
a free running 1
× clock is output.
11: The 1
× clock for the Channel B receiver, which is the clock that
samples the received data. If data is not being received, a free
running 1
× clock is output.
OPCR[1:0] – OP2 Output Select
This field programs the OP2 output to provide one of the following:
00: The complement of OPR[2].
01: The 16
× clock for the Channel A transmitter. This is the clock
selected by CSRA[3:0], and will be a 1
× clock if CSRA[3:0] = 1111.
10: The 1
× clock for the Channel A transmitter, which is the clock
that shifts the transmitted data. If data is not being transmitted,
a free running 1
× clock is output.
11: The 1
× clock for the Channel A receiver, which is the clock that
samples the received data. If data is not being received, a free
running 1
× clock is output.
Table 4.
Bit Rate Generator Characteristics
Crystal or Clock = 3.6864MHz
NORMAL RATE
(BAUD)
ACTUAL 16
×
CLOCK (kHz)
ERROR (%)
50
0.8
0
75
1.2
0
110
1.759
–0.069
134.5
2.153
0.059
150
2.4
0
200
3.2
0
300
4.8
0
600
9.6
0
1050
16.756
–0.260
1200
19.2
0
1800
28.8
0
2000
32.056
0.175
2400
38.4
0
4800
76.8
0
7200
115.2
0
9600
153.6
0
14.4 k
230.4
0
19.2 k
307.2
0
28.8 k
460.8
0
38.4 k
614.4
0
57.6 k
921.6
0
115.2 k
1843.2 k
0
NOTE:
Duty cycle of 16
× clock is 50% ± 1%.
Rates will change in direct proportion to to the X1 rate of 3.6864 MHz.
Asynchronous UART communications can tolerate frequency error
of 4.1% to 6.7% in a ‘clean’ communications channel. The percent of
error changes as the character length changes. The above
percentages range from 5 bits not parity to 8 bits with parity and one
stop bit. The error with 8 bits not parity and one stop bit is 4.6%. If a
stop bit length of 9/16 is used, the error tolerance will approach 0
due to a variable error of up to 1/16 bit time in receiver clock phase
alignment to the start bit.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCC68681C1A44-T | 功能描述:UART 接口集成電路 RPLCMNT FOR SCN68681 RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SCC68681C1N40 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual asynchronous receiver/transmitter |
| SCC68681C1N40,112 | 功能描述:UART 接口集成電路 2CH.UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SCC68681C1N40112 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
| SCC68681E1A44 | 功能描述:UART 接口集成電路 RPLCMNT FOR SCN68681 RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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