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參數(shù)資料
| 型號(hào)： | SCC2691AC1N24,602 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 2/25頁(yè) |
| 文件大小： | 0K |
| 描述： | IC UART SINGLE 24-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Stand-Alone UARTs |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 特點(diǎn)： | 故障啟動(dòng)位檢測(cè) |
| 通道數(shù)： | 1，UART |
| FIFO's： | 3 位 |
| 電源電壓： | 5V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-DIP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 828 (CN2011-ZH PDF) |
| 其它名稱： | 568-1213-5 933811540602 SCC2691AC1N24 |
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Philips Semiconductors
Product data sheet
SCC2691
Universal asynchronous receiver/transmitter (UART)
2006 Aug 04
10
parity mode is programmed. In the special wake-up mode, it selects
the polarity of the transmitted A/D bit.
MR1[1:0] – Bits Per Character Select
This field selects the number of data bits per character to be
transmitted and received. The character length does not include the
start, parity, and stop bits.
MR2 – Mode Register 2
MR2 is accessed when the channel MR pointer points to MR2,
which occurs after any access to MR1. Accesses to MR2 do not
change the pointer.
MR2[7:6] – Mode Select
The UART can operate in one of four modes. MR2[7:6] = 00 is the
normal mode, with the transmitter and receiver operating
independently. MR2[7:6] = 01 places the channel in the automatic
echo mode, which automatically re-transmits the received data. The
following conditions are true while in automatic echo mode:
1. Received data is re-clocked and retransmitted on the TxD
output.
2. The receive clock is used for the transmitter.
3. The receiver must be enabled, but the transmitter need not be
enabled.
4. The TxRDY and TxEMT status bits are inactive.
5. The received parity is checked, but is not regenerated for
transmission, i.e., transmitted parity bit is as received.
6. Character framing is checked, but the stop bits are retransmitted
as received.
7. A received break is echoed as received until the next valid start
bit is detected.
8. CPU-to-receiver communication continues normally, but the
CPU-to-transmitter link is disabled.
Two diagnostic modes can also be selected. MR2[7:6] = 10 selects
local loopback mode. In this mode:
1. The transmitter output is internally connected to the receiver
input.
2. The transmit clock is used for the receiver.
3. The TxD output is held high.
4. The RxD input is ignored.
5. The transmitter must be enabled, but the receiver need not be
enabled.
6. CPU to transmitter and receiver communications continue
normally.
The second diagnostic mode is the remote loopback mode, selected
by MR2[7:6] = 11. In this mode:
1. Received data is re-clocked and retransmitted on the TxD
output.
2. The receive clock is used for the transmitter.
3. Received data is not sent to the local CPU, and the error status
conditions are inactive.
4. The received parity is not checked and is not regenerated for
transmission, i.e., the transmitted parity bit is as received.
5. The receiver must be enabled, but the transmitter need not be
enabled.
6. Character framing is not checked, and the stop bits are
retransmitted as received.
7. A received break is echoed as received until the next valid start
bit is detected.
When switching in and out of the various modes, the selected mode
is activated immediately upon mode selection, even if this occurs in
the middle of a received or transmitted character. Likewise, if a
mode is deselected, the device will switch out of the mode
immediately. An exception to this is switching out of auto-echo or
remote loopback modes; if the deselection occurs just after the
receiver has sampled the stop bit (indicated in auto-echo by
assertion o fRxRDY), and the transmitter is enabled, the transmitter
is enabled, the transmitter will remain in auto-echo mode until one
full stop bit has been retransmitted.
MR2[5] – Transmitter Request-to–Send Control
CAUTION: When the transmitter controls the OP pin (usually used
for the RTSN signal) the meaning of the pin is not RTSN at all!
Rather, it signals that the transmitter has finished the transmission
(i.e., end of block).
This bit allows deactivation of the RTSN output by the transmitter.
This output is manually asserted and negated by the appropriate
commands issued via the command register. MR2[5] set to 1
caused the RTSN to be reset automatically one bit time after the
character(s) in the transmit shift register and in the THR (if any) are
completely transmitted (including the programmed number of stop
bits) if a previously issued transmitter disable is pending. This
feature can be used to automatically terminate the transmission as
follows:
1. Program the auto-reset mode: MR2[5]=1
2. Enable transmitter, if not already enabled
3. Assert RTSN via command
4. Send message
5. After the last character of the message is loaded to the THR,
disable the transmitter. (If the transmitter is underrun, a special
case exists. See note below.)
6. The last character will be transmitted and the RTSN will be reset
one bit time after the last stop bit is sent.
NOTE: The transmitter is in an underrun condition when both the
TxRDY and the TxEMT bits are set. This condition also exists
immediately after the transmitter is enabled from the disabled or
reset state. When using the above procedure with the transmitter in
the underrun condition, the issuing of the transmitter disable must be
delayed from the loading of a single, or last, character until the
TxRDY becomes active again after the character is loaded.
MR2[4] – Clear-to-Send Control
The sate of this bit determines if the CTSN input (MPI) controls the
operation of the transmitter. If this bit is 0, CTSN has no effect on the
transmitter. If this bit is a 1, the transmitter checks the sate of CTSN
each time it is ready to send a character. If it is asserted (low), the
character is transmitted. If it is negated (high), the TxD output
remains in the marking state and the transmission is delayed until
CTSN goes low. Changes in CTSN while a character is being
transmitted do not affect the transmission of that character. This
feature can be used to prevent overrun of a remote receiver.
MR2[3:0] – Stop Bit Length Select
This field programs the length of the stop bit appended to the
transmitted character. Stop bit lengths of 9/16 to 1 and 1–9/16 to 2
bits, in increments of 1/16 bit, can be programmed for character
lengths of 6, 7, and 8 bits. For a character length of 5 bits, 1–1/16 to
2 stop bits can be programmed in increments of 1/16 bit. In all
cases, the receiver only checks for a mark condition at the center of
the first stop bit position (one bit time after the last data bit, or after
the parity bit if parity is enabled). If an external 1X clock is used for
the transmitter, MR2[3] = 0 selects one stop bit and MR2[3] = 1
selects two stop bits to be transmitted.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCC2691AC1N24-S | 功能描述:UART 接口集成電路 5V INDSTRL UART 1 C RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SCC2691AE1A28 | 制造商:PHILIPS-SEMI 功能描述: |
| SCC2691AE1A28,512 | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SCC2691AE1A28,518 | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SCC2691AE1A28,602 | 功能描述:UART 接口集成電路 5V INDSTRL UART 1 C RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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