TIMING DIAGRAMS
參數(shù)資料
型號(hào): SCC2681AC1N40,112
廠商: NXP Semiconductors
文件頁數(shù): 16/29頁
文件大小: 0K
描述: IC UART DUAL 40-DIP
產(chǎn)品培訓(xùn)模塊: Stand-Alone UARTs
標(biāo)準(zhǔn)包裝: 9
特點(diǎn): 故障啟動(dòng)位檢測(cè)
通道數(shù): 2,DUART
FIFO's: 3 位
電源電壓: 5V
帶并行端口:
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測(cè)功能:
帶CMOS:
安裝類型: 通孔
封裝/外殼: 40-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 40-DIP
包裝: 管件
其它名稱: 568-3525-5
935274523112
SCC2681AC1N40
Philips Semiconductors
Product data
SCC2681
Dual asynchronous receiver/transmitter (DUART)
2004 Apr 06
23
TIMING DIAGRAMS (Continued)
NOTES:
1. INTRN or OP3 – OP7 when used as interrupt outputs.
2. The test for open-drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from themidpoint of the switching signal, VM, to a
point 0.5V above VOL. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and test environment are pronounced
and can greatly affect the resultant measurement.
VM
VOL +0.5V
VOL
RDN
OR
WRN
INTERRUPT1
OUTPUT
tIR
SD00090
Figure 6. Interrupt Timing
X1/CLK
CTCLK
RxC
TxC
tCLK
tCTC
tRx
tTx
tCLK
tCTC
tRx
tTx
+5 V
1 k
X1
X2
C1 = C2 = 24 pF FOR CL = 20 pF
X1
X2
3.6864 MHz
3 pF
4 pF
50 TO
150 k
TO INTERNAL CLOCK DRIVERS
SCC2681
NOTE:
C1 AND C2 SHOULD BE BASED ON MANUFACTURER’S SPECIFICATION. PARASITIC CAPACITANCE SHOULD
BE INCLUDED WITH C1 AND C2. R1 IS ONLY REQUIRED IF U1 WILL NOT DRIVE TO X1 INPUT LEVELS
TYPICAL CRYSTAL SPECIFICATION
FREQUENCY:
2 – 4 MHz
LOAD CAPACITANCE (CL):
12 – 32 pF
TYPE OF OPERATION:
PARALLEL RESONANT, FUNDAMENTAL MODE
NC
R1
U1
SD00724
RESISTOR REQUIRED
WHEN U1 IS A TTL DEVICE
Figure 7. Clock Timing
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