參數(shù)資料
型號(hào)： SCC2681AC1A44,529
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 10/29頁(yè)
文件大?。?/td> 0K
描述： IC DUART 44-PLCC
標(biāo)準(zhǔn)包裝： 26
特點(diǎn)： 故障啟動(dòng)位檢測(cè)
通道數(shù)： 2，DUART
FIFO's： 3 位
電源電壓： 5V
帶并行端口： 是
帶自動(dòng)流量控制功能： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC
包裝： 管件
其它名稱： 935274521529
SCC2681AC1A44-S
SCC2681AC1A44-S-ND
Philips Semiconductors
Product data
SCC2681
Dual asynchronous receiver/transmitter (DUART)
2004 Apr 06
18
OPCR – Output Port Configuration Register
OPCR[7] – OP7 Output Select
This bit programs the OP7 output to provide one of the following:
0 – The complement of OPR[7].
1 – The Channel B transmitter interrupt output which is the
complement of TxRDYB. When in this mode OP7 acts as an
Open-drain output. Note that this output is not masked by the
contents of the IMR.
OPCR[6] – OP6 Output Select
This bit programs the OP6 output to provide one of the following:
0 – The complement of OPR[6].
1 – The Channel A transmitter interrupt output which is the
complement of TxRDYA. When in this mode OP6 acts as an
Open-drain output. Note that this output is not masked by the
contents of the IMR.
OPCR[5] – OP5 Output Select
This bit programs the OP5 output to provide one of the following:
0 – The complement of OPR[5].
1 – The Channel B transmitter interrupt output which is the
complement of ISR[5]. When in this mode OP5 acts as an
Open-drain output. Note that this output is not masked by the
contents of the IMR.
OPCR[4] – OP4 Output Select
This field programs the OP4 output to provide one of the following:
0 – The complement of OPR[4].
1 – The Channel B transmitter interrupt output which is the
complement of ISR[1]. When in this mode OP4 acts as an
Open-drain output. Note that this output is not masked by the
contents of the IMR.
OPCR[3:2] – OP3 Output Select
This bit programs the OP3 output to provide one of the following:
00 – The complement of OPR[3].
01 – The counter/timer output, in which case OP3 acts as an
Open-drain output. In the timer mode, this output is a square
wave at the programmed frequency. In the counter mode, the
output remains HIGH until terminal count is reached, at which
time it goes LOW. The output returns to the HIGH state when
the counter is stopped by a stop counter command. Note that
this output is not masked by the contents of the IMR.
10 – The 1
× clock for the Channel B transmitter, which is the clock
that shifts the transmitted data. If data is not being transmitted,
a free running 1
× clock is output.
11 – The 1
× clock for the Channel B receiver, which is the clock that
samples the received data. If data is not being received, a free
running 1
× clock is output.
OPCR[1:0] – OP2 Output Select
This field programs the OP2 output to provide one of the following:
00 – The complement of OPR[2].
01 – The 16
× clock for the Channel A transmitter. This is the clock
selected by CSRA[3:0], and will be a 1
× clock if
CSRA[3:0] = 1111.
10 – The 1
× clock for the Channel A transmitter, which is the clock
that shifts the transmitted data. If data is not being transmitted,
a free running 1
× clock is output.
11 – The 1
× clock for the Channel A receiver, which is the clock that
samples the received data. If data is not being received, a free
running 1
× clock is output.
ACR – Auxiliary Control Register
ACR[7] – Baud Rate Generator Set Select
This bit selects one of two sets of baud rates to be generated by the
BRG:
Set 1:
50, 110, 134.5, 200, 300, 600, 1.05 k, 1.2 k, 2.4 k, 4.8 k,
7.2 k, 9.6 k, and 38.4 k baud.
Set 2:
75, 110, 134.5, 150, 300, 600, 1.2 k, 1.8 k, 2.0 k, 2.4 k,
4.8 k, 9.6 k, and 19.2 k baud.
Please see Table 5 for rates to 115.2 k baud.
The selected set of rates is available for use by the Channel A and
B receivers and transmitters as described in CSRA and CSRB.
Baud rate generator characteristics are given in Table 3.
ACR[6:4] – Counter/Timer Mode And Clock Source Select
This field selects the operating mode of the counter/timer and its
clock source as shown in Table 4.
Table 4.
ACR 6:4 Field Definition
ACR 6:4
MODE
CLOCK SOURCE
000
Counter
External (IP2)
001
Counter
TxCA – 1
× clock of Channel A
transmitter
010
Counter
TxCB – 1
× clock of Channel B
transmitter
011
Counter
Crystal or external clock (X1/CLK)
divided by 16
100
Timer
(square wave)
External (IP2)
101
Timer
(square wave)
External (IP2) divided by 16
110
Timer
(square wave)
Crystal or external clock (X1/CLK)
111
Timer
(square wave)
Crystal or external clock (X1/CLK)
divided by 16
NOTE: Timer mode generates a squarewave.
ACR[3:0] – IP3, IP2, IP1, IP0 Change-of-State Interrupt Enable
This field selects which bits of the input port change register (IPCR)
cause the input change bit in the interrupt status register (ISR[7]) to
be set. If a bit is in the ‘on’ state the setting of the corresponding bit
in the IPCR will also result in the setting of ISR[7], which results in
the generation of an interrupt output if IMR[7] = 1. If a bit is in the
‘off’ state, the setting of that bit in the IPCR has no effect on ISR[7].
IPCR – Input Port Change Register
IPCR[7:4] – IP3, IP2, IP1, IP0 Change-of-State
These bits are set when a change-of-state, as defined in the input
port section of this data sheet, occurs at the respective input pins.
They are cleared when the IPCR is read by the CPU. A read of
the IPCR also clears ISR[7], the input change bit in the interrupt
status register. The setting of these bits can be programmed to
generate an interrupt to the CPU.
IPCR[3:0] – IP3, IP2, IP1, IP0 Current State
These bits provide the current state of the respective inputs. The
information is unlatched and reflects the state of the input pins at the
time the IPCR is read.
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