參數(shù)資料
型號(hào): SCANSTA476
廠商: National Semiconductor Corporation
英文描述: Eight Input IEEE 1149.1 Analog Voltage Monitor
中文描述: IEEE 1149.1標(biāo)準(zhǔn)8個(gè)模擬輸入電壓監(jiān)視器
文件頁(yè)數(shù): 2/7頁(yè)
文件大?。?/td> 502K
代理商: SCANSTA476
Connection Diagram
20083522
DAP = GND
(Top View)
Pin Descriptions
Pin No.
ANALOG I/O
16
15
14
13
12
11
10
9
2
Symbol
Description
A0
A1
A2
A3
A4
A5
A6
A7
V
REF
Analog input 0. This signal can range from 0V to V
REF
.
Analog input 1. This signal can range from 0V to V
REF
.
Analog input 2. This signal can range from 0V to V
REF
.
Analog input 3. This signal can range from 0V to V
REF
.
Analog input 4. This signal can range from 0V to V
REF
.
Analog input 5. This signal can range from 0V to V
REF
.
Analog input 6. This signal can range from 0V to V
REF
.
Analog input 7. This signal can range from 0V to V
REF
.
Analog reference voltage input. V
REF
must be
V
DD
. This pin should be connected to a quiet
+2.7V to +5.5V source (not directly to V
DD
) and bypassed to GND with 0.1 μF and 1 μF
monolithic capacitors located within 1 cm of the V
REF
pin.
DIGITAL I/O
6
5
7
8
4
POWER SUPPLY
TDI
TDO
TMS
TCK
TRST
Test Data Input to support IEEE 1149.1 features
Test Data Ouput to support IEEE 1149.1 features
Test Mode Select to support IEEE 1149.1 features
Test Clock to support IEEE 1149.1 features
Test Reset to support IEEE 1149.1 features
1,3
V
DD
Positive supply pin. These pins should be connected to a quiet +2.7V to +5.5V source and
bypassed to GND with 0.1 μF and 1 μF monolithic capacitors located within 1 cm of the
power pin.
Ground reference for CMOS circuitry. DAP is the exposed metal contact at the bottom of the
LLP package. The DAP is used as the primary GND connection to the device. It should be
connected to the ground plane with at least 4 vias for optimal low-noise and thermal
performance.
(Note 1)
GND
Note 1:
Note that GND is not an actual pin on the package, the GND is connected thru the DAP on the back side of the LLP package.
S
www.national.com
2
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