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參數(shù)資料
| 型號： | SCANSTA112VS |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 300K |
| 代理商： | SCANSTA112VS |
TABLE 1. Pin Descriptions
Pin Name
VCC
GND
RESET
ADDMASK
MPsel
B1/B0
Description
No.
Pins
10
10
1
1
1
I/O
N/A
N/A
I
I
I
Power
Ground
RESET Input: will force a reset of the device regardless of the current state.
ADDRESS MASK input: Allows masking of lower slot input pins.
MASTER PORT SELECTION: Controls selection of LSP
B0
or LSP
B1
as the backplane port.
The unselected port becomes LSP
00
. A value of "0" will select LSP
B0
as the master port.
Selects ScanBridge or Stitcher Mode.
In Stitcher Mode these inputs define which LSP’s are to be included in the scan chain
Transparent Mode enable input: The value of this pin is loaded into the TRANSENABLE bit
of the control register at power-up. This value is used to control the presence of registers
and pad-bits in the scan chain while in the stitcher mode.
Sets the driven value of TRST
0-5
when LSP TAPs are in TLR and the device is not being
reset. During RESET = "0" or TRST
B
= "0" (IgnoreReset = "0") TRST
n
= "0". This pin is to be
tied low to match the function of the SCANSTA111
This pin affects TRST of LSP
6
only. This pin is to be tied low to match the function of the
SCANSTA111
BACKPLANE TEST DATA INPUT: All backplane scan data is supplied to the ’STA112
through this input pin. MPsel
B1/B0
determines which port is the master backplane port and
which is LSP
00
. This input has a 25K
internal pull-up resistor and no ESD clamp diode
(ESD is controlled with an alternate method). When the device is power-off (V
DD
floating),
this input appears to be a capacitive load to ground (Note 1). When V
DD
= 0V (i.e.; not
floating but tied to V
SS
) this input appears to be a capacitive load with the pull-up to ground.
BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP Controller of the
’STA112. Also controls sequencing of the TAPs which are on the local scan chains.
MPsel
B1/B0
determines which port is the master backplane port and which is LSP
00
. This
bidirectional TRISTATE pin has 24mA of drive current, with a 25K
internal pull-up resistor
and no ESD clamp diode (ESD is controlled with an alternate method). When the device is
power-off (V
DD
floating), this input appears to be a capacitive load to ground (Note 1). When
V
DD
= 0V (i.e.; not floating but tied to V
SS
) this input appears to be a capacitive load with the
pull-up to ground.
BACKPLANE TEST DATA OUTPUT: This output drives test data from the ’STA112 and the
local TAPs, back toward the scan master controller. This bidirectional TRISTATE pin has
12mA of drive current. MPsel
B1/B0
determines which port is the master backplane port and
which is LSP
00
. Output is sampled during interrogation addressing. When the device is
power-off (V
DD
= 0V or floating), this output appears to be a capacitive load (Note 1).
TEST CLOCK INPUT FROM THE BACKPLANE: This is the master clock signal that controls
all scan operations of the ’STA112 and of the local scan ports. MPsel
B1/B0
determines which
port is the master backplane port and which is LSP
00
. These bidirectional TRISTATE pins
have 24mA of drive current with hysterisis. This input has no pull-up resistor and no ESD
clamp diode (ESD is controlled with an alternate method). When the device is power-off (V
DD
floating), this input appears to be a capacitive load to ground (Note 1). When V
DD
= 0V (i.e.;
not floating but tied to V
SS
) this input appears to be a capacitive load to ground.
TEST RESET: An asynchronous reset signal (active low) which initializes the ’STA112 logic.
MPsel
B1/B0
determines which port is the master backplane port and which is LSP
00
. This
bidirectional TRISTATE pin has 24mA of drive current, with a 25K
internal pull-up resistor
and no ESD clamp diode (ESD is controlled with an alternate method). When the device is
power-off (V
DD
floating), this pin appears to be a capacitive load to ground (Note 1). When
V
DD
= 0V (i.e.; not floating but tied to V
SS
) this input appears to be a capacitive load with the
pull-up to ground.
SB/S
LSPsel
(0-6)
TRANS
1
7
1
I
I
I
TLR_TRST
1
I
TLR_TRST
6
1
I
TDI
B0
, TDI
B1
2
I
TMS
B0
, TMS
B1
2
I/O
TDO
B0
, TDO
B1
2
I/O
TCK
B0
, TCK
B1
2
I/O
TRST
B0
, TRST
B1
2
I/O
S
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCANSTA112VS/NOPB | 功能描述:編碼器、解碼器、復用器和解復用器 7-port Multidrop Mux RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| SCANSTA112VS/NOPB | 制造商:Texas Instruments 功能描述:, Termination:Solder, Package/Case:100-T |
| SCANSTA112VSX | 功能描述:編碼器、解碼器、復用器和解復用器 RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| SCANSTA112VSX/NOPB | 功能描述:編碼器、解碼器、復用器和解復用器 RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| SCANSTA476 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Eight Input IEEE 1149.1 Analog Voltage Monitor |
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