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參數(shù)資料
| 型號： | SCANSTA112 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer |
| 中文描述： | 7端口多點的IEEE 1149.1（JTAG接口）多路復(fù)用 |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 300K |
| 代理商： | SCANSTA112 |
TABLE 1. Pin Descriptions
(Continued)
Pin Name
TRIST
B0
, TRIST
B1
Description
No.
Pins
2
I/O
O
BACKPLANE TRI-STATE NOTIFICATION OUTPUT: This signal is high when the backplane
scan port is TRI-STATEd. This pin is used for backplane physical layer changes (i.e.; TTL to
LVDS). This TRISTATE output has 12mA of drive current. MPsel
B1/B0
determines which port
is the master backplane port and which is LSP
00
.
BACKPLANE PASS-THROUGH INPUT: A general purpose input which is driven to the Y
n
of
a single selected LSP. (Not available when multiple LSPs are selected). This input has a
25K
internal pull-up resistor. MPsel
B1/B0
determines which port is the master backplane
port and which is LSP
00
.
BACKPLANE PASS-THROUGH OUTPUT: A general purpose output which is driven from
the A
n
of a single selected LSP. (Not available when multiple LSPs are selected). This
TRISTATE output has 12mA of drive current. MPsel
B1/B0
determines which port is the master
backplane port and which is LSP
00
.
SLOT IDENTIFICATION: The configuration of these pins is used to identify (assign a unique
address to) each ’STA112 on the system backplane
OUTPUT ENABLE for the Local Scan Ports, active low. When high, this active-low control
signal TRI-STATEs all local scan ports on the ’STA112, to enable an alternate resource to
access one or more of the local scan chains.
TEST DATA OUTPUTS: Individual output for each of the local scan ports . These TRISTATE
outputs have 12mA of drive current.
TEST DATA INPUTS: Individual scan data input for each of the local scan ports. This input
has a 25K
internal pull-up resistor.
TEST MODE SELECT OUTPUTS: Individual output for each of the local scan ports. TMS
n
does not provide a pull-up resistor (which is assumed to be present on a connected TMS
input, per the IEEE 1149.1 requirement) . These TRISTATE outputs have 24mA of drive
current.
LOCAL TEST CLOCK OUTPUTS: Individual output for each of the local scan ports. These
are buffered versions of TCK
B
. These TRISTATE outputs have 24mA of drive current.
LOCAL TEST RESETS: A gated version of TRST
B
. These TRISTATE outputs have 24mA of
drive current.
LOCAL PASS-THROUGH INPUTS: General purpose inputs which can be driven to the
backplane pin Y
B
. (Only on LSP
0
and LSP
1
. Only available when a single LSP is selected) .
These inputs have a 25K
internal pull-up resistor.
LOCAL PASS-THROUGH OUTPUT: General purpose outputs which can be driven from the
backplane pin A
B
. (Only on LSP
0
and LSP
1
. Only available when a single LSP is selected) .
These TRISTATE outputs have 12mA of drive current.
LOCAL TRI-STATE NOTIFICATION OUTPUTS: This signal is high when the local scan ports
are TRI-STATEd . These pins are used for backplane physical layer changes (i.e.; TTL to
LVDS). These TRISTATE outputs have 12mA of drive current.
A0
B0
, A1
B0
, A0
B1
,
A1
B1
4
I
Y0
B0
, Y1
B0
, Y0
B1
,
Y1
B1
4
O
S
(0-7)
8
I
OE
1
I
TDO
(01-06)
6
O
TDI
(01-06)
6
I
TMS
(01-06)
6
O
TCK
(01-06)
6
O
TRST
(01-06)
6
O
A0
01
, A1
01
2
I
Y0
01
, Y1
01
2
O
TRIST
(01-03)
3
O
Note 1:
Refer to the IBIS model on our website for I/O characteristics.
Application Overview
ADDRESSING SCHEME
- The SCANSTA112 architecture
extends the functionality of the IEEE 1149.1 Standard by
supplementing that protocol with an addressing scheme
which allows a test controller to communicate with specific
’STA112s within a network of ’STA112s. That network can
include both multi-drop and hierarchical connectivity. In ef-
fect, the ’STA112 architecture allows a test controller to
dynamically select specific portions of such a network for
participation in scan operations. This allows a complex sys-
tem to be partitioned into smaller blocks for testing purposes.
The ’STA112 provides two levels of test-network partitioning
capability. First, a test controller can select individual
’STA112s, specific sets of ’STA112s (multi-cast groups), or
all ’STA112s (broadcast). This ’STA112-selection process is
supported by a Level-1 communication protocol. Second,
within each selected ’STA112, a test controller can select
one or more of the chip’s seven local scan-ports. That is,
individual local ports can be selected for inclusion in the
(single) scan-chain which a ’STA112 presents to the test
controller. This mechanism allows a controller to select spe-
cific scan-chains within the overall scan network. The port-
selection process is supported by a Level-2 protocol.
HIERARCHICAL SUPPORT
- Multiple SCANSTA112’s can
be used to assemble a hierarchical boundary-scan tree. In
S
www.national.com
7
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCANSTA112_05 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:7-Port Multidrop IEEE 1149.1 (JTAG) Multiplexer |
| SCANSTA112EVK | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 SCANSTA112 EVAL KIT RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| SCANSTA112EVK/NOPB | 功能描述:界面開發(fā)工具 SCANSTA112 EVAL KIT RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| SCANSTA112SM | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| SCANSTA112SM/NOPB | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 7-port Multidrop Mux RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
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