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參數(shù)資料
| 型號： | SCAN926260TUFX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST |
| 中文描述： | HEX LINE RECEIVER, PBGA196 |
| 封裝： | LBGA-196 |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 372K |
| 代理商： | SCAN926260TUFX |
Application Information
USING THE SCAN926260
The SCAN926260 combines six 1:10 deserializers into a
single chip. Each of the six deserializers accepts a BusLVDS
data stream up to 660 Mbps from one of National Semicon-
ductor’s 10-Bit Serializers. The Deserializers then recover
the embedded two clock bits and data to deliver the resulting
10-bit wide words to the output. The Deserializer uses a
separate reference clock (REFCLK) and an on-board PLL to
extract the clock information from the incoming data stream
and then deserialize the data. The Deserializer monitors the
incoming clock information, determines lock status, and as-
serts the LOCKn output high when loss of lock occurs.
POWER CONSIDERATIONS
An all CMOS design of the Deserializer makes it an inher-
ently low power device.
POWERING UP THE DESERIALIZER
The SCAN926260 can be powered up at any time. The
REFCLK input can be running before the Deserializer pow-
ers up, and it must be running in order for the Deserializer to
lock
to
incoming
data.
(ROUTn[0:9]), the recovered clock (RCLKn), and LOCKn are
high until the Deserializer detects data transmission at its
inputs and locks to the incoming data stream.
The
Deserializer
outputs
DATA TRANSFER
Once the Deserializer powers up, it must be phase locked to
the transmitter to transfer data. Phase locking occurs when
the Deserializer locks to incoming data or when the Serial-
izer sends sync patterns. The Serializer sends SYNC pat-
terns whenever the SYNC1 or SYNC2 inputs are high. The
LOCKn output of the Deserializer remains high until it has
locked to the incoming data stream. Connecting the LOCKn
output of the Deserializer to one of the SYNC inputs of the
Serializer will guarantee that enough SYNC patterns are
sent to achieve Deserializer lock.
The Deserializer can also lock to incoming data by simply
powering up the device and allowing the “l(fā)ock to pseudo
random data” circuitry to find and lock to the data stream.
While the Deserializer LOCKn output is low, data at the
respective channel’s Deserializer outputs (ROUTn[0:9]) is
valid, except for the specific case when loss of lock occurs
during transmission which is further discussed in the "Recov-
ering from LOCK Loss" section below.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter
(phase noise) that the Deserializer can tolerate and still
reliably receive data. Various environmental and systematic
factors include:
Serializer: TCLK jitter, V
DD
noise (noise bandwidth and
out-of-band noise)
Media: ISI, Large V
CM
shifts
Deserializer: V
DD
noise
Please see the section on "Using t
RNM
to Validate Signal
Quality" for more information.
RECOVERING FROM LOCK LOSS
In the case where the Deserializer loses lock during data
transmission, up to 1 cycle of data that was previously
received can be invalid. This is due to the delay in the lock
detection circuit. The lock detect circuit requires that invalid
clock information be received two times in a row to indicate
loss of lock. Since clock information has been lost, it is
possible that data was also lost during these cycles. There-
fore, after the Deserializer relocks to the incoming data
stream and the Deserializer LOCKn pin goes low, at least
one previous data cycle should be suspect for bit errors.
The Deserializer can relock to the incoming data stream by
making the Serializer resend SYNC patterns, as described
above, or by locking to pseudo random data, which can take
more time, depending on the data patterns being received.
HOT INSERTION
All Bus LVDS Deserializers are hot pluggable if you follow a
few rules. When inserting, ensure the Ground pin(s) makes
contact first, then the VCC pin(s), and then the I/O pins.
When removing, the I/O pins should be unplugged first, then
the VCC, then the Ground. Random lock hot insertion is
illustrated in
Figure 9
.
TRANSMISSION MEDIA
The Serializer and Deserializer can also be used in point-to-
point configurations, through PCB trace, through twisted pair
cable, or twinax cables. In point-to-point configurations, the
transmission media need only be terminated at the receiver
end. Please note that in point-to-point configurations, the
potential of offsetting the ground levels of the Serializer vs.
the Deserializer must be considered. In some applications,
multidrop configurations may be possible. Bus LVDS pro-
vides a
±
1.0V common mode range at the receiver inputs.
FAILSAFE BIASING FOR THE SCAN926260
The SCAN926260 has internal failsafe biasing and an im-
proved input threshold sensitivity of
±
50mV versus
±
100mV
for the DS92LV1210.. This allows for a greater differential
noise margin. However, in cases where the receiver input is
not being actively driven, the increased sensitivity of the
SCAN926260 can pickup noise as a signal and cause unin-
tentional locking. For example, this can occur when an input
cable is disconnected.
External resistors can be added to the receiver circuit board
to boost the level of failsafe biasing. Typically, the non-
inverting receiver input is pulled up and the inverting receiver
input is pulled down by high value resistors. The pull-up and
pull-down resistors (R
1
and R
2
) provide a current path
through the termination resistor (R
L
) which biases the re-
ceiver inputs when they are not connected to an active
driver. The value of the pull-up and pull-down resistors
should be chosen so that enough current is drawn to provide
a +15mV minimum drop across the termination resistor in
the presence of anticipated input noise. Also, in systems
20028315
FIGURE 9. Hot Insertion Lock to Pseudo-Random Data
S
www.national.com
12
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PDF描述 |
|---|---|
| SCAN928028 | 8 Channel 10:1 Serializer with IEEE 1149.1 and At-Speed BIST |
| SCAN928028TUF | 8 Channel 10:1 Serializer with IEEE 1149.1 and At-Speed BIST |
| SCAN928028TUFX | 8 Channel 10:1 Serializer with IEEE 1149.1 and At-Speed BIST |
| SCAN92LV090 | 9 Channel Bus LVDS Transceiver with 1149.1 Access |
| SCAN92LV090SLC | 9 Channel Bus LVDS Transceiver w/ Boundary SCAN |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SCAN926260TUFX/NOPB | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SCAN928028 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8 Channel 10:1 Serializer with IEEE 1149.1 and At-Speed BIST |
| SCAN928028TUF | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SCAN928028TUF/NOPB | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SCAN928028TUFX | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
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