參數(shù)資料
型號(hào): SCAN921260UJBX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: X6 1:10 Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST
中文描述: HEX LINE RECEIVER, PBGA196
封裝: LBGA-196
文件頁(yè)數(shù): 15/16頁(yè)
文件大?。?/td> 379K
代理商: SCAN921260UJBX
Pin Descriptions
(Continued)
Pin Name
Type
Pins
Description
TMS
CMOS
Input
CMOS
Input
CMOS
Input
CMOS
Input
CMOS
Output
CMOS
Input
C1
Test Mode Select input to support IEEE
1149.1
TRST
C2
Test Reset Input to support IEEE 1149.1
TDI
D1
Test Data Input to support IEEE 1149.1
TCK
D2
Test Clock to support IEEE 1149.1
TDO
D3
Test Data Output to support TDO
BISTMODE_REQ
B10
BIST Alone Error Reporting Mode Select
Input
These pins control which channels are
active for the BIST Alone operation mode.
The BIST Alone Mode Selection Table
describes their function. There are internal
pull-ups that default all BIST_SEL(0:2) to
high, which is the idle state for all channels
in BIST Alone mode.
A high on this input enables the CHTST
output. There is an internal pull-up that
defaults the CHTST output to the active
mode. Note: CHTEST_EN requires two
clock cycles before CHTST is enabled or
disabled. When not using CHTST output,
assert a low on this control pin to reduce
power consumption.
A high on this pin activates the BIST Alone
operating mode. There is a weak internal
pull-down that should default the BIST_ACT
to de-activate the BIST Alone operating
mode. In a noisy operating environment, it is
recommended that an external pull down be
used to ensure that BIST_ACT is in the low
state.
Unused solder ball location. Do not connect.
BIST_SEL(0:2)
CMOS
Input
C14, D8, D14
CHTST_EN
CMOS
Input
E3
BIST_ACT
CMOS
Input
K11
N/C
E11, F11, L4, L5
S
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SCAN921821 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1(JTAG), and At-Speed BIST
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