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參數(shù)資料
| 型號： | SCAN921226 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST |
| 中文描述： | 30-80 MHz的10位總線LVDS串行解串器與IEEE 1149.1（JTAG）及在速度BIST |
| 文件頁數(shù)： | 20/21頁 |
| 文件大?。?/td> | 474K |
| 代理商： | SCAN921226 |
Deserializer Pin Description
Pin Name
I/O
O
Ball Id.
A5, B4, B6,
C4, C7, D6,
F5, F7, G4,
G5
B3
Description
ROUT
Data Output.
±
9 mA CMOS level outputs.
RCLKR/F
I
Recovered Clock Rising/Falling strobe select. TTL level input.
Selects RCLK active edge for strobing of ROUT data. High
selects rising edge. Low selects falling edge.
+ Serial Data Input. Non-inverting Bus LVDS differential input.
Serial Data Input. Inverting Bus LVDS differential input.
Powerdown. TTL level input. PWRDN driven low shuts down the
PLL and TRI-STATEs outputs putting the device into a low power
sleep mode.
LOCK goes low when the Deserializer PLL locks onto the
embedded clock edge. CMOS level output. Totem pole output
structure, does not directly support wired OR connections.
Recovered Clock. Parallel data rate clock recovered from
embedded clock. Used to strobe ROUT, CMOS level output.
Output Enable. TTL level input. When driven low, TRI-STATEs
ROUT0–ROUT9 and RCLK.
Digital Circuit power supply.
RI+
RI
PWRDN
I
I
I
D2
C1
D3
LOCK
O
E1
RCLK
O
E2
REN
I
D1
DVCC
I
A7, B7, C5,
C6, D5
A1, A6, B5,
D7, E4, E7,
G3
B1, C2, F1,
F2, G1
A4, B2, F3,
F4, G2
A3
DGND
I
Digital Circuit ground.
AVCC
I
Analog power supply (PLL and Analog Circuits).
AGND
I
Analog ground (PLL and Analog Circuits).
REFCLK
I
Use this pin to supply a REFCLK signal for the internal PLL
frequency.
Test Data Input to support IEEE 1149.1. There is an internal
pullup resistor that defaults this input to high per IEEE 1149.1.
Test Data Output to support IEEE 1149.1
Test Mode Select Input to support IEEE 1149.1. There is an
internal pullup resistor that defaults this input to high per IEEE
1149.1.
Test Clock Input to support IEEE 1149.1
Test Reset Input to support IEEE 1149.1. There is an internal
pullup resistor that defaults this input to high per IEEE 1149.1.
Leave open circuit, do not connect
TDI
I
F6
TDO
TMS
O
I
G6
G7
TCK
TRST
I
I
E5
E6
N/C
N/A
A2, C3, D4,
E3
Deserializer Truth Table
INPUTS
OUTPUTS
LOCK
PWRDN
H (4)
H
L
H
REN
H
H
X
L
ROUT [0:9]
Z
Active
Z
Z
RCLK
Z
Active
Z
Z
H
L
Z
Active
1) LOCK Active indicates the LOCK output will reflect the state of the Deserializer with regard to the selected data stream.
2) RCLK Active indicates the RCLK will be running if the Deserializer is locked. The Timing of RCLK with respect to ROUT is determined by RCLK_R/F.
3) ROUT and RCLK are TRI-STATED when LOCK is asserted High.
4) During Power-up.
S
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCAN921226H | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST |
| SCAN921226HSM | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SCAN921226HSM/NOPB | 功能描述:LVDS 接口集成電路 High Tem 20MHz-80 MHz 10B Serializer RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SCAN921226HSMX | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SCAN921226HSMX/NOPB | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
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