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參數(shù)資料
| 型號： | SCAN921025SLC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST |
| 中文描述： | LINE DRIVER, PBGA49 |
| 封裝： | FBGA-49 |
| 文件頁數(shù)： | 15/21頁 |
| 文件大?。?/td> | 474K |
| 代理商： | SCAN921025SLC |
Application Information
Using the SCAN921025 and SCAN921226
The Serializer and Deserializer chipset is an easy to use
transmitter and receiver pair that sends 10 bits of parallel
LVTTL data over a serial Bus LVDS link up to 800 Mbps. An
on-board PLLserializes the input data and embeds two clock
bits within the data stream. The Deserializer uses a separate
reference clock (REFCLK) and an onboard PLL to extract
the clock information from the incoming data stream and
then deserialize the data. The Deserializer monitors the
incoming clock information, determines lock status, and as-
serts the LOCK output high when loss of lock occurs.
Power Considerations
An all CMOS design of the Serializer and Deserializer makes
them inherently low power devices. In addition, the constant
current source nature of the Bus LVDS outputs minimizes
the slope of the speed vs. I
CC
curve of conventional CMOS
designs.
Powering Up the Deserializer
The SCAN921226 can be powered up at any time by follow-
ing the proper sequence. The REFCLK input can be running
before the Deserializer powers up, and it must be running in
order for the Deserializer to lock to incoming data. The
Deserializer outputs will remain in TRI-STATE until the De-
serializer detects data transmission at its inputs and locks to
the incoming data stream.
Transmitting Data
Once you power up the Serializer and Deserializer, they
must be phase locked to each other to transmit data. Phase
locking occurs when the Deserializer locks to incoming data
or when the Serializer sends patterns. The Serializer sends
SYNC patterns whenever the SYNC1 or SYNC2 inputs are
high. The LOCK output of the Deserializer remains high until
it has locked to the incoming data stream. Connecting the
LOCK output of the Deserializer to one of the SYNC inputs of
the Serializer will guarantee that enough SYNC patterns are
sent to achieve Deserializer lock.
The Deserializer can also lock to incoming data by simply
powering up the device and allowing the “random lock”
circuitry to find and lock to the data stream.
While the Deserializer LOCK output is low, data at the De-
serializer outputs (ROUT0-9) is valid, except for the specific
case of loss of lock during transmission which is further
discussed in the ’Recovering from LOCK Loss’ section be-
low.
Noise Margin
The Deserializer noise margin is the amount of input jitter
(phase noise) that the Deserializer can tolerate and still
reliably receive data. Various environmental and systematic
factors include:
Serializer: TCLK jitter, V
CC
noise (noise bandwidth and
out-of-band noise)
Media: ISI, Large V
CM
shifts
Deserializer: V
CC
noise
Recovering from LOCK Loss
In the case where the Deserializer loses lock during data
transmission, up to 3 cycles of data that were previously
received can be invalid. This is due to the delay in the lock
detection circuit. The lock detect circuit requires that invalid
clock information be received 4 times in a row to indicate
loss of lock. Since clock information has been lost, it is
possible that data was also lost during these cycles. There-
fore, after the Deserializer relocks to the incoming data
stream and the Deserializer LOCK pin goes low, at least
three previous data cycles should be suspect for bit errors.
The Deserializer can relock to the incoming data stream by
making the Serializer resend SYNC patterns, as described
above, or by random locking, which can take more time,
depending on the data patterns being received.
Hot Insertion
All the BLVDS devices are hot pluggable if you follow a few
rules. When inserting, ensure the Ground pin(s) makes con-
tact first, then the VCC pin(s), and then the I/O pins. When
removing, the I/O pins should be unplugged first, then the
VCC, then the Ground. Random lock hot insertion is illus-
trated in Figure 21
PCB Considerations
The Bus LVDS Serializer and Deserializer should be placed
as close to the edge connector as possible. In multiple
Deserializer applications, the distance from the Deserializer
to the slot connector appears as a stub to the Serializer
driving the backplane traces. Longer stubs lower the imped-
ance of the bus, increase the load on the Serializer, and
lower the threshold margin at the Deserializers. Deserializer
devices should be placed much less than one inch from slot
connectors. Because transition times are very fast on the
Serializer Bus LVDS outputs, reducing stub lengths as much
as possible is the best method to ensure signal integrity.
Transmission Media
The Serializer and Deserializer can also be used in
point-to-point configuration of a backplane, through a PCB
trace, or through twisted pair cable. In point-to-point configu-
ration, the transmission media need only be terminated at
the receiver end. Please note that in point-to-point configu-
ration, the potential of offsetting the ground levels of the
Serializer vs. the Deserializer must be considered. Also, Bus
LVDS provides a +/ 1.2V common mode range at the
receiver inputs.
Failsafe Biasing for the SCAN921226
The SCAN921226 has an improved input threshold sensitiv-
ity of +/ 50mV versus +/ 100mV for the DS92LV1210 or
DS92LV1212. This allows for greater differential noise mar-
gin in the SCAN921226. However, in cases where the re-
ceiver input is not being actively driven, the increased sen-
sitivity of the SCAN921226 can pickup noise as a signal and
cause unintentional locking. For example, this can occur
when the input cable is disconnected.
External resistors can be added to the receiver circuit board
to prevent noise pick-up. Typically, the non-inverting receiver
input is pulled up and the inverting receiver input is pulled
down by high value resistors. the pull-up and pull-down
resistors (R
and R
) provide a current path through the
termination resistor (R
) which biases the receiver inputs
when they are not connected to an active driver. The value of
the pull-up and pull-down resistors should be chosen so that
enough current is drawn to provide a +15mV drop across the
termination resistor. Please see Figure 18 for the Failsafe
Biasing Setup.
Using t
DJIT
and t
RNM
to Validate Signal Quality
The parameter t
is calculated by first measuring how
much of the ideal bit the receiver needs to ensure correct
sampling.After determining this amount, what remains of the
ideal bit that is available for external sources of noise is
called t
RNM
. t
RNM
includes transmitter jitter.
Please refer to Figure 19 and Figure 20 for a graphic repre-
sentation of t
DJIT
and t
RNM
. Also, for a more detailed expla-
S
www.national.com
15
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCAN921025SLC/NOPB | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SCAN9212224SLC/NOPB | 制造商:Texas Instruments 功能描述: |
| SCAN921224 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:20-66 MHz 10 Bit Bus LVDS Serializer and Deserializer |
| SCAN9212245LC | 制造商:Texas Instruments 功能描述: |
| SCAN921224SLC | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
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