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參數(shù)資料
| 型號： | SCAN18541TSSC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Non-Inverting Line Driver with 3-STATE Outputs |
| 中文描述： | SCAN/JTAG/3J SERIES, DUAL 9-BIT BOUNDARY SCAN DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 0.300 INCH, MO-118, SSOP-56 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 90K |
| 代理商： | SCAN18541TSSC |
9
www.fairchildsemi.com
S
AC Operating Requirements
Scan Test Operation:
Note:
All Input Timing Delays involving TCK are measured from the rising edge of TCK.
Note 10:
Voltage Range 5.0 is 5.0V
±
0.5V.
Note 11:
This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0-8, 9-17, 18-26 and 27-35.
Note 12:
Timing pertains to BSR 37, 38, 40 and 41 only.
Note 13:
This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only.
Symbol
Parameter
V
CC
T
A
=
+
25
°
C
C
L
=
50 pF
T
A
=
40
°
C to
+
85
°
C
C
L
=
50 pF
Units
(V)
(Note 10)
Guaranteed Minimum
t
S
Setup Time, H or L
5.0
3.0
3.0
ns
Data to TCK (Note 11)
Hold Time, H or L
TCK to Data (Note 11)
t
H
5.0
4.5
4.5
ns
t
S
Setup Time, H or L
AOE
n
, BOE
n
to TCK (Note 12)
Hold Time, H or L
5.0
3.0
3.0
ns
t
H
5.0
4.5
4.5
ns
TCK to AOE
n
, BOE
n
(Note 12)
Setup Time, H or L
Internal AOE, BOE, to TCK (Note 13)
t
S
5.0
3.0
3.0
ns
t
H
Hold Time, H or L
TCK to Internal AOE, BOE (Note 13)
Setup Time, H or L
5.0
3.0
3.0
ns
t
S
5.0
8.0
8.0
ns
TMS to TCK
Hold Time, H or L
TCK to TMS
t
H
5.0
2.0
2.0
ns
t
S
Setup Time, H or L
TDI to TCK
Hold Time, H or L
5.0
4.0
4.0
ns
t
H
5.0
4.5
4.5
ns
TCK to TDI
Pulse Width TCK
t
W
5.0
H
15.0
15.0
ns
L
5.0
5.0
f
MAX
Maximum TCK
5.0
25
25
MHz
Clock Frequency
Wait Time, Power Up
to TCK
T
PU
5.0
100
100
ns
T
DN
Power Down Delay
0.0
100
100
ms
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