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參數(shù)資料
| 型號： | SCAN15MB200TSQX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6 |
| 中文描述： | DUAL LINE TRANSCEIVER, PQCC48 |
| 封裝： | LLP-48 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 599K |
| 代理商： | SCAN15MB200TSQX |
TRI-STATE and Powerdown Modes
The SCAN15MB200 has output enable control on each of
the six onboard LVDS output drivers. This control allows
each output individually to be placed in a low power TRI-
STATE mode while the device remains active, and is useful
to reduce power consumption on unused channels. In TRI-
STATE mode, some outputs may remain active while some
are in TRI-STATE.
When all six of the output enables (all drivers on both chan-
nels) are deasserted (LOW), then the device enters a Pow-
erdown mode that consumes only 0.5mA (typical) of supply
current. In this mode, the entire device is essentially pow-
ered off, including all receiver inputs, output drivers and
internal bandgap reference generators. When returning to
active mode from Powerdown mode, there is a delay until
valid data is presented at the outputs because of the ramp to
power up the internal bandgap reference generators.
Any single output enable that remains active will hold the
device in active mode even if the other five outputs are in
TRI-STATE.
When in Powerdown mode, any output enable that becomes
active will wake up the device back into active mode, even if
the other five outputs are in TRI-STATE.
Input Failsafe Biasing
External pull up and pull down resistors may be used to
provide enough of an offset to enable an input failsafe under
open-circuit conditions. This configuration ties the positive
LVDS input pin to VDD thru a pull up resistor and the
negative LVDS input pin is tied to GND by a pull down
resistor. The pull up and pull down resistors should be in the
5k
to 15k
range to minimize loading and waveform dis-
tortion to the driver. Please refer to application note AN-
1194, “Failsafe Biasing of LVDS Interfaces” for more infor-
mation.
Interfacing LVPECL to LVDS
An LVPECL driver consists of a differential pair with coupled
emitters connected to GND via a current source. This drives
a pair of emitter-followers that require a 50
to V
CC
-2.0 load.
Amodern LVPECL driver will typically include the termination
scheme within the device for the emitter follower. If the driver
does not include the load, then an external scheme must be
used. The 1.3 V supply is usually not readily available on a
PCB, therefore, a load scheme without a unique power
supply requirement may be used.
Figure 3
is a separated
π
termination scheme for a 3.3 V
LVPECL driver. R1 and R2 provides proper DC load for the
driver emitter followers, and may be included as part of the
driver device (Note 17). The 15MB200 includes a 100
input
termination for the transmission line. The common mode
voltage will be at the normal LVPECL levels – around 2 V.
This scheme works well with LVDS receivers that have
rail-to-rail common mode voltage, V
, range. Most National
Semiconductor LVDS receivers have wide V
range. The
exceptions are noted in devices’ respective datasheets.
Those LVDS devices that do have a wide V
range do not
vary in performance significantly when receiving a signal
with a common mode other than standard LVDS V
CM
of 1.2
V.
An AC coupled interface is preferred when transmitter and
receiver ground references differ more than 1 V. This is a
likely scenario when transmitter and receiver devices are on
separate PCBs.
Figure 4
illustrates an AC coupled interface
between a LVPECL driver and LVDS receiver. R1 and R2, if
not present in the driver device (Note 17), provide DC load
for the emitter followers and may range between 140-220
for most LVPECL devices for this particular configuration.
The 15MB200 includes an internal 100
resistor to termi-
nate the transmission line for minimal reflections. The signal
after ac coupling capacitors will swing around a level set by
internal biasing resistors (i.e. fail-safe) which is either V
/2
or 0 V depending on the actual failsafe implementation. If
internal biasing is not implemented, the signal common
mode voltage will slowly drift to GND level.
20132861
FIGURE 3. DC Coupled LVPECL to LVDS Interface
20132862
FIGURE 4. AC Coupled LVPECL to LVDS Interface
S
www.national.com
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參數(shù)描述 |
|---|---|
| SCAN15MB200TSQX/NOPB | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SCAN15MB200TSQXNOPB | 制造商:National Semiconductor 功能描述:LVDS Repeater 0.5V 48-Pin LLP EP T/R |
| SCAN162512ASM | 制造商:Texas Instruments 功能描述:BUS TRANSCEIVER 16BIT IEEE 162512 |
| SCAN162512ASM/NOPB | 功能描述:IC UNIV BUS TXRX 16BIT 64FBGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 通用總線函數(shù) 系列:SCAN 產(chǎn)品變化通告:Product Discontinuation 09/Dec/2010 標(biāo)準(zhǔn)包裝:1,500 系列:74AVC 邏輯類型:通用總線驅(qū)動器 輸入數(shù):- 電路數(shù):18 位 輸出電流高，低:12mA，12mA 電源電壓:1.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:56-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:56-TSSOP 包裝:帶卷 (TR) |
| SCAN162512SM | 功能描述:IC UNIV BUS TXRX 16BIT 64FBGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - 通用總線函數(shù) 系列:SCAN 產(chǎn)品變化通告:Product Discontinuation 09/Dec/2010 標(biāo)準(zhǔn)包裝:1,500 系列:74AVC 邏輯類型:通用總線驅(qū)動器 輸入數(shù):- 電路數(shù):18 位 輸出電流高，低:12mA，12mA 電源電壓:1.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:56-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:56-TSSOP 包裝:帶卷 (TR) |
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