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參數(shù)資料
| 型號： | SC8164 |
| 廠商： | Vitesse Semiconductor Corporation. |
| 英文描述： | 2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux |
| 中文描述： | 2.488 Gb /秒的2.7Gbit/sec 1:16的SONET / SDH解復(fù)用 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 153K |
| 代理商： | SC8164 |
VITESSE
SEMICONDUCTOR CORPORATION
reliminary Datasheet
SC8164
2.488 Gbit/sec to 2.7Gbit/sec
1:16 SONET/SDH Demux
G52239-0, Rev. 3.3
VITESSE SEMICONDUCTOR CORPORATION
Page 3
5/17/00
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
High Speed Interface
The incoming 2.488Gb/s data (up to 2.7Gb/s for FEC applications) and input clock are received by high
speed inputs DI and HSCLKI. The data and clock inputs are internally terminated by a center-tapped resistor
network. For differential input DC coupling, the network is terminated to the appropriate termination voltage
VTerm (pins HSDREF, HSCLKREF) providing a 50 to VTerm termination for both true and complement inputs.
For differential input AC coupling, the network is terminated to VTerm via a blocking capacitor.
In most situations these inputs will have high transition density and little DC offset. However, in cases
where this does not hold, direct DC connection is possible. All serial data and clock inputs have the same circuit
topology, as shown in Figure 4. The reference voltage is created by a resistor divider as shown. If the input sig-
nal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be cen-
tered about this reference voltage and not exceed the maximum allowable amplitude (
V
CMI, VIHSDC). For
single-ended, DC-coupling operations, it is recommended that the user provides an external reference voltage
which has better temperature and power supply noise rejection than the on-chip resistor divider. The external
reference should have a nominal value equivalent to the common mode switch point of the DC coupled signal,
and can be connected to either side of the differential gate.
Figure 4: High Speed Serial Clock and Data Inputs
Supplies
This device is specified as a LVPECL device with a single positive 3.3V supply. Should the user desire to
use the device in a ECL environment with a negative 3.3V supply, then VCC will be ground and VEE will be -
3.3V.
VCC = 3.3V
VEE = 0V
CIN
Chip Boundary
CIN TYP = 100 nF
CAC TYP = 100 nF
ZO
VTerm
CAC
50
50
CIN
ZO
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