328
32072H–AVR32–10/2012
AT32UC3A3
blocks is a function of CTLx.LLP_S_EN, CFGx.RELOAD_SR, CTLx.LLP_D_EN, and
Note:
Both SARx and DARx updates cannot be selected to be contiguous. If this functionality is
required, the size of the Block Transfer (CTLx.BLOCK_TS) must be increased. If this is at the max-
imum value, use Row 10 of
block descriptor to be equal to the end SARx address of the previous block. Similarly, setup the
LLI.DARx address of the block descriptor to be equal to the end DARx address of the previous
block.
19.9.1.4
Suspension of Transfers Between Blocks
At the end of every block transfer, an end of block interrupt is asserted if:
interrupts are enabled, CTLx.INT_EN = 1
the channel block interrupt is unmasked, MaskBlock[n] = 0, where n is the channel number.
Note:
The block complete interrupt is generated at the completion of the block transfer to the destination.
transfers. For example, at the end of block N, the DMACA automatically proceeds to block N + 1.
block transfers), the DMA transfer automatically stalls after the end of block. Interrupt is asserted
if the end of block interrupt is enabled and unmasked.
The DMACA does not proceed to the next block transfer until a write to the block interrupt clear
register, ClearBlock[n], is performed by software. This clears the channel block complete
interrupt.
block transfers), the DMA transfer does not stall if either:
interrupts are disabled, CTLx.INT_EN = 0, or
the channel block interrupt is masked, MaskBlock[n] = 1, where n is the channel number.
Channel suspension between blocks is used to ensure that the end of block ISR (interrupt ser-
vice routine) of the next-to-last block is serviced before the start of the final block commences.
This ensures that the ISR has cleared the CFGx.RELOAD_SR and/or CFGx.RELOAD_DS bits
b e fo re co mp let i on of t h e fina l blo ck. Th e r e lo ad bit s CF Gx .REL OAD _ SR a n d / o r
CFGx.RELOAD_DS should be cleared in the ‘end of block ISR’ for the next-to-last block
transfer.
19.9.2
Ending Multi-block Transfers
At the end of every block transfer, the DMACA samples the row number, and if the DMACA is in
Row 1 or Row 5 state, then the previous block transferred was the last block and the DMA trans-
fer is terminated.
Note:
Row 1 and Row 5 are used for single block transfers or terminating multiblock transfers. Ending in
Row 5 state enables status fetch for the last block. Ending in Row 1 state disables status fetch for
the last block.
CFGx.RELO A D_DS is s e t), m u lti-bloc k DM A tran sfer s co ntinu e un til b o th th e
CFGx.RELOAD_SR and CFGx.RELOAD_DS registers are cleared by software. They should be