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參數(shù)資料
| 型號： | SC80C52XXX-12SB |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | SIDE BRAZED, 40 PIN |
| 文件頁數(shù)： | 19/20頁 |
| 文件大?。?/td> | 194K |
| 代理商： | SC80C52XXX-12SB |
80C32/80C52/80C32E
8
Rev. J
– July 03, 2000
5.4. I/O Ports
The I/O buffers for Ports 1, 2 and 3 are implemented as shown in Figure 4.
Figure 4. I/O Buffers in the 80C52 (Ports 1, 2, 3)
When the port latch contains a 0, all pFETS in figure 4 are off while the nFET is turned on. When the port latch makes
a 0-to-1 transition, the nFET turns off. The strong pFET, T1, turns on for two oscillator periods, pulling the output high
very rapidly. As the output line is drawn high, pFET T3 turns on through the inverter to supply the IOH source current.
This inverter and T form a latch which holds the 1 and is supported by T2.
When Port 2 is used as an address port, for access to external program of data memory, any address bit that contains
a 1 will have his strong pullup turned on for the entire duration of the external memory access.
When an I/O pin on Ports 1, 2, or 3 is used as an input, the user should be aware that the external circuit must sink current
during the logical 1-to-0 transition. The maximum sink current is specified as ITL under the D.C. Specifications. When
the input goes below approximately 2 V, T3 turns off to save ICC current. Note, when returning to a logical 1, T2 is
the only internal pullup that is on. This will result in a slow rise time if the user’s circuit does not force the input line
high.
5.5. Oscillator Characteristics
XTAL1 and XTAL2 are the input and output respectively, of an inverting amplifier which is configured for use as an
on-chip oscillator, as shown in Figure 5. Either a quartz crystal or ceramic resonator may be used.
Figure 5. Crystal Oscillator
To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected as shown
in Figure 6. There are no requirements on the duty cycle of the external clock signal, since the input to the internal
clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on
the Data Sheet must be observed.
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