參數(shù)資料
型號(hào)： SC68C94C1N
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Pressure Transducer, Series 19 mm, Compensated, Pressure Range: 0 psi to 50 psi, Gage, flush mount, 10 Vdc excitation
中文描述： 4 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP48
封裝： PLASTIC, DIP-48
文件頁(yè)數(shù)： 24/33頁(yè)
文件大?。?/td> 215K
代理商： SC68C94C1N
Philips Semiconductors
Product specification
SC68C94
Quad universal asynchronous receiver/transmitter (QUART)
1995 May 1
24
AC ELECTRICAL CHARACTERISTICS
4
T
A
= 25
°
C; V
CC
= 5V
±
10%, unless otherwise specified. Limits shown as nn/nn refer to Commercial/Industrial temperature range. Single
numbers apply to both ranges.
NO.
FIGURE
CHARACTERISTIC
LIMITS
Typ
UNIT
Min
10
45
Max
1
2
3
4
2
2
2
2
Setup: A[5:0] valid to CEN Low
Hold: A[5:0] valid after CEN Low
6
Access: Later of CEN Low and RDN Low, to Dnn valid (read)
Later of CEN Low and (RDN or WRN as applicable) Low, to DACKN Low
Normal Operation:
ns
ns
ns
ns
110/115
10 + 2
X1 edges
5
90/122 + 3
X1 edges
5
150
30
30
From Power Down:
Earlier of CEN High or RDN High, to Dnn released (read)
1
Earlier of CEN High or (RDN or WRN as applicable) High, to DACKN released
Earlier of CEN High or (RDN or WRN as applicable) High, in one cycle, to later
of CEN Low and (RDN or WRN as applicable) Low, for the next cycle
Setup, Dnn valid (write) to later of CEN Low and WRN Low
2
Later of CEN Low and WRN Low, to earlier of CEN High or WRN High
Hold: Dnn valid (write) after DACKN Low, CEN High or WRN High
3
5
6
2
2
0
0
ns
ns
7
2
50
ns
8
9
10
2
2
2
–30
ns
ns
ns
110/115
0
NOTES:
1. The minimum time indicates that read data will remain valid until the bus master drives CEN and/or RDN to High.
2. The fact that this parameter is negative means that the Dnn line may actually become valid after CEN and WRN are both Low.
3. In a Write operation, the bus master must hold the write data valid either until drives CEN and/or WRN to High, or until the QUART drives
DACKN to Low, whichever comes first.
4. Test condition for interrupt and I/O outputs: C
L
= 50pF, forced current for V
OL
= 5.3mA; forced current for V
OH
= 400
μ
A, RL = 2.7k
to V
CC
.
Test condition for rest of outputs: C
L
= 150pF
5. Consecutive write operations to the upper four bits of the Command Register (CR) require at least three X1/CLK edges; four X1/CLK edges
in the ‘X1/CLK divide by 2 edges’ according to register 2E or 2F setting.
6. Address is latched at leading edge of a read or write cycle.
A[5:0]
CEN
RDN
WRN
D[7:0]
1
2
1
2
READ CYCLE
WRITE CYCLE
DACKN
4
4
3
3
7
7
9
9
7
7
9
9
5
5
6
6
8
8
4
4
10
10
10
6
6
SD00181
Figure 2. A Read Cycle Followed by a Write Cycle with DACKN
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