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參數(shù)資料
| 型號： | SC68C94C1A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | nullQuad universal asynchronous receiver/transmitter QUART |
| 中文描述： | 4 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC52 |
| 封裝： | PLASTIC, SOT-238-3, LCC-52 |
| 文件頁數(shù)： | 28/33頁 |
| 文件大?。?/td> | 215K |
| 代理商： | SC68C94C1A |
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Philips Semiconductors
Product specification
SC68C94
Quad universal asynchronous receiver/transmitter (QUART)
1995 May 1
28
C1 and C2 should be chosen according to the
crystal manufacturer’s specification.
C1 and C2 values will include any parasitic
capacitance of the wiring.
X1/CLK
CTCLK
RxC
TxC
t
CLK
t
CTC
t
Rx
t
Tx
t
CLK
t
CTC
t
Rx
t
Tx
+5V
1K required for
TTL gate.
X1
X2
C1 = C2 = 24pF FOR C
L
= 20PF
X1
X2
3.6864MHz
3pF
4pF
50 KOHMs
TO
150 KOHMs
26C94
NOTES:
C1 and C2 should be based on manufacturer’s specification.
X1 and X2 parasitic capacitance IS 1-2pF AND 3-5pF, respectively.
GAIN:
at 4MHz 8 to 14db; at 8MHz 2 to 6db
PHASE: at 4MHz 272
°
to 276
°
; at 8MHz 272
°
to 276
°
TYPICAL CRYSTAL SPECIFICATION
2 – 4MHZ
12 – 32pF
PARALLEL RESONANT, FUNDAMENTAL MODE
FREQUENCY:
LOAD CAPACITANCE (C
L
):
TYPE OF OPERATION:
NC
C1
C2
MUX
To
remainder
of circuit
÷
2
38.4kHz CLOCK
BRG
TO I/O CHANGE-OF-STATE DETECTORS
22
STANDARD
RATES
SD00172
Figure 10. Clock Timing
TxC
(INPUT)
TxD
TxC
(1X OUTPUT)
1 BIT TIME
(1 OR 16 CLOCKS
t
TCS
t
TXD
SD00173
Figure 11. Transit Clock Timng
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