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參數(shù)資料
| 型號(hào)： | SC68C94A1A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | nullQuad universal asynchronous receiver/transmitter QUART |
| 中文描述： | 4 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC52 |
| 封裝： | PLASTIC, SOT-238-3, LCC-52 |
| 文件頁(yè)數(shù)： | 30/33頁(yè) |
| 文件大?。?/td> | 215K |
| 代理商： | SC68C94A1A |
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Philips Semiconductors
Product specification
SC68C94
Quad universal asynchronous receiver/transmitter (QUART)
1995 May 1
30
D1
D2
D9
D10
D11
D12
D13
D3
RxD
RECEIVER
ENABLED
RxRDY
(SR0)
FFULL
(SR1)
RxRDY/
FFULL
ISR(1)
RDN
OVERRUN
(SR4)
1
RTS
NOTES;
1. TIMING SHOWN FOR MR1[7] = 1.
2. DEFAULT: I/O1 IS RTS AND IOPCR(5:4)
≠
01
I/O1 = 1 or (CR[7:4] = 1010)
RESET BY
COMMAND
D10 WILL
BE LOST
S
D
S
D
S
D
S
D
D2
D3
D10
D1
S = STATUS
D = DATA
D2
D10 WILL BE
OVERWRITTEN
BY D11, 12, ETC
SD00176
Figure 14. Receiver Data Timing
MASTER STATION
TxD
TRANSMITTER
ENABLED
TxRDY
(SR2)
CEN
(WRITE]
PERIPHERAL STATION
RxD
RECEIVER
ENABLED
RxRDY
(SR0)
RDN/WRN
ADD#1
1
D0
0
ADD#2
1
BIT 9
BIT 9
BIT 9
BIT 9
BIT 9
BIT 9
BIT 9
BIT 9
MR1 [4:3] = 11
MR1 [2] = 1
ADD#1
MR1 [2] = 0
D0
MR1 [2] = 1
ADD#2
0
ADD#1
1
D0
0
ADD#2
1
0
MR1 [4:3] = 11
ADD#1
D0
S
D
S = STATUS
D = DATA
S
D
ADD#2
NOTE: TIMING SHOWN FOR FIFO POWER-UP DEFAULT
SD00177
Figure 15. Wake-Up Mode
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