參數(shù)資料
型號: SC68C562A8A
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Pressure Transducer, Series 19 mm, Compensated, Pressure Range: 0 psi to 50 psi, Absolute, flush mount with flange, 10 Vdc excitation
中文描述: 2 CHANNEL(S), 8M bps, MULTI PROTOCOL CONTROLLER, PQCC52
封裝: PLASTIC, LCC-52
文件頁數(shù): 3/26頁
文件大?。?/td> 163K
代理商: SC68C562A8A
Philips Semiconductors
Product specification
SC68C562
CMOS Dual universal serial communications controller
(CDUSCC)
1998 Sep 04
3
1X or 16X Rx and Tx clock factors
Parity, overrun, and framing error detection
False start bit detection
Start bit search 1/2-bit time after framing error detection
Break generation with handshake for counting break characters
Detection of start and end of received break
Character compare with optional interrupt on match
Transmits up to 10Mb/s at 1X and receive up to 1Mb/s at 16X
data rates
Character-Oriented Protocol Features
Character length: 5 to 8 bits
Odd or even parity, no parity, or force parity
LRC or CRC generation and checking
Optional opening PAD transmission
One or two SYN characters
External sync capability
SYN detection and optional stripping
SYN or MARK line fill on underrun
Idle in MARK or SYNs
Parity, FCS, overrun, and underrun error detection
BISYNC Features
EBCDIC or ASCII header, text and control messages
SYN, DLE stripping
EOM (end of message) detection and transmission
Auto transparent mode switching
Auto hunt after receipt of EOM sequence (with closing PAD check
after EOT or NAK)
Control character sequence detection for both transparent and
normal text
Bit-Oriented Protocol Features
Character length: 5 to 8 bits
Detection and transmission of residual character: 0–7 bits
Automatic switch to programmed character length for I field
Zero insertion and deletion
Optional opening PAD transmission
Detection and generation of FLAG, ABORT, and IDLE bit patterns
Detection and generation of shared (single) FLAG between
frames
Detection of overlapping (shared zero) FLAGs
ABORT, ABORT-FLAGs, or FCS FLAGs line fill on underrun
Idle in MARK or FLAGs
Secondary address recognition including group and global
address
Single- or dual-octet secondary address
Extended address and control fields
Short frame rejection for receiver
Detection and notification of received end of message
CRC generation and checking
SDLC loop mode capability
ORDERING INFORMATION
DESCRIPTION
V
CC
= +5V
±
10%,
T
A
= 0 to +70
°
C
Serial Data Rate =
10Mbps Maximum
SC68C562C1N
V
CC
= +5V
±
10%,
T
A
= –40 to +85
°
C
Serial Data Rate =
8Mbps Maximum
Not available
DWG #
48-Pin Plastic Dual In-Line Package (DIP)
SOT240-1
52-Pin Plastic Leaded Chip Carrier (PLCC) Package
SC68C562C1A
SC68C562A8A
SOT238-3
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
PARAMETER
RATING
UNIT
COMMERCIAL
0 to +70
-65 to +150
–0.5 to +7.0
–0.5 to V
CC
+0.5
INDUSTRIAL
-40 to +85
-65 to +150
–0.5 to +7.0
–0.5 to V
CC
+0.5
T
A
T
STG
V
CC
V
S
Operating ambient temperature
2
Storage temperature
Voltage from V
CC
to GND
3
Voltage from any pin to ground
3
°
C
°
C
V
V
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