參數(shù)資料
型號(hào)： SC68C198C1A
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Pressure Transducer, Series 19 mm, Compensated, Pressure Range: 0 psi to 50 psi, Absolute, flush mount, 10 Vdc excitation
中文描述： 8 CHANNEL(S), 500K bps, SERIAL COMM CONTROLLER, PQCC84
封裝： PLASTIC, LCC-84
文件頁(yè)數(shù)： 22/49頁(yè)
文件大?。?/td> 358K
代理商： SC68C198C1A
Philips Semiconductors
Product specification
SC26C198 SC68C198
SC26L198 SC68L198
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
1995 May 1
357
SR[0] – Receiver Ready (RxRDY)
This bit indicates that a character has been received and is waiting
in the RxFIFO to be read by the CPU. It is set when the character is
transferred from the receive shift register to the RxFIFO and reset
when the CPU reads the RxFIFO, and no more characters are in the
RxFIFO.
change of
a UART channel. When generating an interrupt arbitration value,
the contents of this register are masked by the interrupt mask
register (IMR). If a bit in the ISR is a ’1’ and the corresponding bit in
the IMR is also a ’1’, interrupt arbitration for this source will begin. If
the corresponding bit in the IMR is a zero, the state of the bit in the
ISR can have no affect on the IRQN output. Note that the IMR may
or may not mask the
reading
of the ISR as determined by MR1[6].
If MR1[6] is cleared, the reset and power on default, the ISR is read
without modification. If MR1[6] is set, the a read of the ISR gives a
value of the ISR ANDed with the IMR.
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Watch-dog
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recognition event
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event
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Break State
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Receiver has entered
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Transmitter has entered
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The general function of this bit is to indicate that the RxFIFO has
data available. The particular meaning of this bit is programmed by
MR2[3:2]. If programmed as receiver ready(MR2[3:2] = 00), it
indicates that at least one character has been received and is
waiting in the RxFIFO to be read by the host CPU. It is set when the
character is transferred from the receive shift register to the RxFIFO
and reset when the CPU reads the last character from the RxFIFO.
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ISR[7] – Input Change of State
This bit is set when a change of state occurs at the I/O1 or I/O0
input pins. It is reset when the CPU reads the Input Port Register,
IPR.
ISR[6] Watch-dog Time–out
This bit is set when the receiver’s watch-dog timer has counted
more than 64 bit times since the last RxFIFO event. RxFIFO events
are a read of the RxFIFO or GRxFIFO, or the push of a received
character into the FIFO. The interrupt will be cleared automatically
upon the push of the next character received or when the RxFIFO or
GRxFIFO is read. The receiver watch-dog timer is included to allow
detection of the very last characters of a received message that may
be waiting in the RxFIFO, but are too few in number to successfully
initiate an interrupt. Refer to the watch-dog timer description for
details of how the interrupt system works after a watch-dog
time–out.
ISR[5] – Address Recognition Status Change
This bit is set when a change in receiver state has occurred due to
an Address character being received from an external source and
comparing to the reference address in ARCR. The bit and interrupt
is negated by a write to the CR with command x11011, Reset
Address Recognition Status.
ISR[4] – Xon/Xoff Status Change
This bit is set when an Xon/Xoff character being received from an
external source. The bit is negated by a read of the channel Xon
Interrupt Status Register, XISR.
ISR[3] – Reserved
Always reads a 0
ISR[2] – Change in Channel Break Status
This bit, when set, indicates that the receiver has detected the
beginning or the end of a received break. It is reset when the CPU
If MR2[3:2] is programmed as FIFO full, ISR[1] is set when a
character is transferred from the receive holding register to the
RxFIFO and the transfer causes the RxFIFO to become full, i.e. all
sixteen FIFO positions are occupied. It is reset when ever RxFIFO
is not full. If there is a character waiting in the receive shift register
because the FIFO is full, the bit is set again when the waiting
character is transferred into the FIFO.
The other two conditions of these bits, 3/4 and half full operate in a
similar manner. The ISR[1] bit is set when the RxFIFO fill level
meets or exceeds the value; it is reset when the fill level is less.
See the description of the MR2 register.
Note: This bit must be at a one (1) for the receiver to enter the
arbitration process. It is the fact that this bit is zero (0) when the
RxFIFO is empty that stops an empty FIFO from entering the
interrupt arbitration. Also note that the meaning if this bit is not quite
the same as the similar bit in the status register (SR).
ISR[0] – Transmitter Ready
The general function of this bit is to indicate that the TxFIFO has an
at least one empty space for data. The particular meaning of the bit
is controlled by MR0[5:4] indicates the TxFIFO may be loaded with
one or more characters. If MR0[5:4] = 00 (the default condition) this
bit will not set until the TxFIFO is empty – sixteen bytes available. If
the fill level of the TxFIFO is below the trigger level programmed by
the TxINT field of the Mode Register 0, this bit will be set. A one in
this position indicates that at least one character can be sent to the
TxFIFO. It is turned off as the TxFIFO is filled above the level
programmed by MR0[5:4. This bit turns on as the FIFO empties; the
RxFIFO bit turns on as the FIFO fills. This often a point of confusion
in programming interrupt functions for the receiver and transmitter
FIFOs.
Note: This bit must be at a one (1) for the transmitter to enter the
arbitration process. It is the fact that this bit is zero (0) when the
RxFIFO is full that stops a full FIFO from entering the interrupt
arbitration. Also note that the meaning if this bit is not quite the
of state
Time–out
The programming of this register selects which bits in the ISR cause
an interrupt output. If a bit in the ISR is a ’1’ and the corresponding
bit in the IMR is a ’1’, the interrupt source is presented to the internal
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recognition event
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Break State
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interrupt
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interrupt
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interrupt arbitration circuits, eventually resulting in the IRQN output
being asserted (low). If the corresponding bit in the IMR is a zero,
the state of the bit in the ISR has no affect on the IRQN output.
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相關(guān)PDF資料
PDF描述
SC68L198 Octal UART with TTL compatibility at 3.3V and 5V supply voltages
SC68L198A1A Pressure Transducer, Series 19 mm, Compensated, Pressure Range: 0 psi to 50 psi, Gage, flush mount with flange, 10 Vdc excitation
SC68L198C1A Octal UART with TTL compatibility at 3.3V and 5V supply voltages
SC28C94 Quad universal asynchronous receiver/transmitter QUART
SC28C94A1N Quad universal asynchronous receiver/transmitter QUART
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SC68C2550BIB48,128 功能描述:UART 接口集成電路 2.5V-5V 2CH UART 16B RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC68C2550BIB48,151 功能描述:UART 接口集成電路 UART DUAL W/FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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