Device User Guide — 9S12DT128DGV2/D V02.15
107
Freescale Semiconductor
A.2 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
A.2.1 ATD Operating Characteristics
The (Table A-8) shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive
beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped.
Table A-8 ATD Operating Characteristics
A.2.2 Factors influencing accuracy
Three factors – source resistance, source capacitance and current injection – have an influence on the
accuracy of the ATD.
A.2.2.1 Source Resistance:
Due to the input pin leakage current as specified in (Table A-6) in conjunction with the source resistance
there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS
Conditions are shown in (Table A-4) unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
D
Reference Potential
Low
High
VRL
VRH
VSSA
VDDA/2
VDDA
V
2
C Differential Reference Voltage1
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.50V
VRH-VRL
4.50
5.00
5.25
V
3
D ATD Clock Frequency
fATDCLK
0.5
2.0
MHz
4
D
ATD 10-Bit Conversion Period
Clock Cycles2
Conv, Time at 2.0MHz ATD Clock fATDCLK
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
NCONV10
TCONV10
14
7
28
14
Cycles
s
5
D
ATD 8-Bit Conversion Period
Conv, Time at 2.0MHz ATD Clock fATDCLK
NCONV8
TCONV8
12
6
26
13
Cycles
s
6
D Stop Recovery Time (VDDA=5.0 Volts)
tSR
20
s
7
P Reference Supply current (Both ATD modules on)
IREF
0.75
mA
8
P Reference Supply current (Only one ATD module on)
IREF
0.375
mA