參數(shù)資料
型號: SC26C94A1N
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Quad universal asynchronous receiver/transmitter QUART
中文描述: 4 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP48
封裝: PLASTIC, DIP-48
文件頁數(shù): 23/33頁
文件大?。?/td> 211K
代理商: SC26C94A1N
Philips Semiconductors
Product specification
SC26C94
Quad universal asynchronous receiver/transmitter (QUART)
1995 May 1
23
AC ELECTRICAL CHARACTERISTICS
5, 6, 7, 8
SYMBOL
FIGURE
PARAMETER
LIMITS
Typ
UNIT
Min
Max
Reset timing
t
RES
I/O Port timing
t
PS
t
PH
7
Reset pulse width
200
ns
8
8
I/O input setup time before RDN Low
I/O input hold time after RDN High
I/O output valid from
WRN High
RDN Low
0
0
ns
ns
t
PD
8
110
110
ns
ns
Interrupt timing
t
IR
9
IRQN negated or I/O output High from:
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY interrupt)
Reset command (break change interrupt)
Reset command (I/O change interrupt)
Stop C/T command (counter interrupt)
Write IMR (clear of interrupt mask bit)
With respect to a
3.6864MHz clock
on pin X1/CLK
100
100
100
100
100
100
ns
ns
ns
ns
ns
ns
Clock timing
t
CLK
t
CLK
t
CLK
t
CTC
f
CTC
t
RX
10
10
10
10
10
10
X1/CLK low/high time
X1/CLK low/high time (above 4MHz; X1/CLK
÷
2 active)
X1/CLK frequency
Counter/timer clock high or low time
Counter/timer clock frequency
RxC high or low time
RxC frequency (16X)
RxC frequency (1X)
TxC high or low time
TxC frequency (16X)
TxC frequency (1X)
125/100
56/56
0
9
60
0
9
30
0
9
0
9
30
0
9
0
9
ns
ns
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz
3.6864
8.0
8
f
RX
10
16
1.0
t
TX
10
f
TX
10
16
1.0
Transmitter timing
t
TXD
t
TCS
Receiver timing
t
RXS
t
RXH
NOTES:
1. Stress above these listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only.
Functional operation of the device at these or any other condition above those indicated in the operation section of the specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on +150
o
C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range. See ordering information table for applicable temperature range and operating
supply range.
5. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 20ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of V
IL
and V
IH
, as
appropriate.
6. Typical values are at +25
o
C, typical supply voltages, and typical processing parameters.
7. Test condition for interrupt and I/O outputs: C
= 50pF, R
= 2.7k
to V
. Test conditions for rest of outputs: C
= 150pF.
8. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. CEN
and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated
first terminates the cycle.
9. This value is not tested, but is guaranteed by design. For t
CLK
minimum test rate is 2.0MHz.
11
11
TxD output delay from TxC low
TxC output delay from TxD output data
120
+20
ns
ns
–20
12
12
RxD data setup time to RxC high
RxD data hold time from RxC high
100
100
ns
ns
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