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參數(shù)資料
| 型號： | SC2677TSTRT |
| 廠商： | Semtech Corporation |
| 英文描述： | Dual Synchronous Voltage Mode Controller with Current Sharing Circuitry |
| 中文描述： | 雙同步電壓模式控制器的電流共享電路 |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 163K |
| 代理商： | SC2677TSTRT |
8
2004 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
Applications Information
SC2677
for best design, often a more optimum layout can be
achieved by keeping the wide trace and using proper layer
stacking to minimize the stray inductance.
It is important to keep the gate traces short, the IC must
be close to the power switches. It is recommended to
use at least 25 mil width or wider trace when ever
possible. A good placement can help if the controller is
placed in the middle of the two PWM channels.
Grounding requirements are always important in a buck
converter layout, especially at high power. Power ground
(PGND) should be returned to the bottom MOSFET source
to provide the best gate current return path. Analog
ground (GND) shape should be used for the anaglog re-
turns such as chip decoupling, frequency setiing, refer-
ence voltage (or soft starting cap), and the compensation.
This groung shap should be single point connected to
the PGND shape near the ground side of the output
capacitors. This will provide noise free analog ground for
operation stablity, and also provide best possible re-
mote sensing for the feedback voltage. In case two
output rails need to be regulated, the AGND shape should
single point connected to the geometrica center of the
PGND for the two point of loads. The single ponit tie is a
must to prevent the power current from flowing on the
AGND shape, so that the analog circuitry in the control-
ler has an electrically quiet reference and to provide the
greatest noise free operation. Keep in mind that the
AGND pin is never allowed to have bigger than 1V volt-
age difference vs the PGND pin. This usually achievable
by using a ground plan for PGND in PCB layout. Using
ground plane for PGND can reduce the physical separa-
tion between the two grounds, such that even the fast
current transitions in the PGND plane can not generate
voltage spikes exceeding the 1V level, therefore prevent-
ing unstable and erratic behavior from happening.
The feedback divider must be close to the IC and be
returned to analog ground. Current sense traces must
be run parallel and close to each other and to analog
ground.
The IC must have a ceramic decoupling capacitor across
its supply pins, mounted as close to the device as
possible. The small ceramic, noise-filtering capacitors on
the current sense lines should also be placed as close to
the IC as possible.
Shutdown
The output short circuit protection is done by output
undervoltage detection. Upon output short circuit and
when the output voltage drops bellow a certain percent-
age of the regulation target (see elctrical characteristics
table for details, the PWM will be disabled and the out-
put will be dsiabbled and latched off. The latch can be
reset by power cycling.
Layout Guidelines
Power and signal traces must be kept separated for noise
considerations. Feedback, current sense traces and ana-
log ground should not cross any traces or planes carrying
high switching currents, such as in the input loop or the
phase node.
The input loop, consisting of the input capacitors and
both MOSFETs must be kept as small as possible. Since
all of the high switching currents occur in the input loop,
the enclosed loop area must be kept small to minimize
inductance and radiated and conducted noise emissions.
Designing for minimum trace length is not the only factor
(R13+R19) vs.Oscillator Frequency
300
400
500
600
700
800
900
1000
4
6
8
10
12
14
16
18
20
(R13+R19) (kohm)
O
Vphasing vs Phase Shift
0
20
40
60
80
100
120
140
160
180
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
Vphasing (V)
P
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