參數(shù)資料
型號: SC2596
廠商: Semtech Corporation
英文描述: Low Voltage Integrated DDR Termination Regulator
中文描述: 低電壓集成DDR終端穩(wěn)壓器
文件頁數(shù): 10/13頁
文件大小: 300K
代理商: SC2596
10
2007 Semtech Corp.
www.semtech.com
SC2596
PRELIMINARY
POWER MANAGEMENT
Application Information (Cont.)
Application_2: Lower Power Loss Configuration for
SSTL-2
If power loss is a major concern, separating the PVCC
form AVCC and VDDQ will be a good choice (Figure 2).
The PVCC can operate at lower voltage (1.8V to 2.5V) if
2.5V voltage is applied on AVCC and the VDDQ, the source
current is lower due to the lower operating voltage ap-
plied on the PVCC.
Figure 2: Lower power loss for SSTL-2(DDR-I).
Application_3: High Source Current Configuration
If there is a need for VTT to source more current, espe-
cially for DDR-II applications, the system designer can tie
the AVCC and PVCC to 3.3V while has the VDDQ tie to 1.
8V. This configuration can ensure more than 2A source
and sink capability from the VTT rail.
Figure 4: High current set up for SSTL-18(DDR-II).
Notes:
(a) The preferred configuration for DDR-I applications
is to tie AVCC and PVCC to VDDQ, which is typically 2.5V.
(b) If AVCC and PVCC rails are tied together, then the
VDDQ cannot lead the AVCC and PVCC.
Figure 3: Lower power loss for SSTL-18(DDR-II).
C
10nF
EN
VDDQ
1.8V
0.9V
0.9V
Cout
220uF
Cin1
1uF
SC2596
GND
1
EN
2
VSENSE
3
VREF
4
VDDQ
5
AVCC
6
PVCC
7
VTT
8
VTT
Cin2
100uF
Cref
100nF
VREF
0
2.5V
1M
C
10nF
EN
0.9V
VDDQ
1.8V
0.9V
Cout
220uF
Cin1
1uF
SC2596
GND
1
EN
2
VSENSE
3
VREF
4
VDDQ
5
AVCC
6
PVCC
7
VTT
8
VTT
Cin2
100uF
Cref
100nF
VREF
0
3.3V
VREF
Cout
220uF
C
10nF
2.5V
1.25V
VTT
Cin1
100uF
EN
Cref
100nF
Cin2
1uF
0
SC2596
GND
1
EN
2
VSENSE
3
VREF
4
VDDQ
5
AVCC
6
PVCC
7
VTT
8
1.25V
VDDQ
2.5V
PVCC
2.5V
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參數(shù)描述
SC2596_09 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Low Voltage Integrated DDR Termination Regulator
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