參數(shù)資料
型號: SC2441
廠商: Semtech Corporation
英文描述: Very Low Input Voltage 2-Phase Synchronous Step-down Controllers with Step-up Converter
中文描述: 非常低的輸入電壓2相同步降壓與升壓轉(zhuǎn)換器控制器
文件頁數(shù): 20/35頁
文件大?。?/td> 733K
代理商: SC2441
20
2005 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
Applications Information (Cont.)
SC2441
Q1
Q2
Cin
Cou t
RL
Rload
Rs
Vo
Vin
Cs
vC (t)
L
iL(t)
Q 3
Q 4
VP N
Vbe4
Vbe3
Vgs2
Vgs1
PN
Figure 12. The basic structure of combi-sense.
follow the gate drive signals Vgs1 and Vgs2 respectively
with minimal delay. The transition edges at the Virtual
Phase Node (VPN) therefore matches closely to those of
the Phase Node (PN).
When Q1/Q3 are on and Q2/Q4 are off, the circuit in Figure
12 is reduced to that of Figure 13 a). Here Rds1 is the on-
resistance of the top MOSFET. The branches {(Rds1+RL),
L} and {R
, C
}, are in parallel. The DC voltage across L and
the DC current through C
are both zero. There is no DC
voltage across R
s
either. Therefore on average, the voltage
drop (Rds1+RL)I
o
equals V
. The DC inductor current can
be sensed from V
Cs
if (Rds1+RL) is known.
When Q1/Q3 are off and Q2/Q4 are on, the equivalent
circuit of Figure 12 reduces to the sub-circuit in Figure
13b). Here Rds2 is the channel resistance of the bottom
MOSFET. In this case, the branch {R
s
, C
} is in parallel with
{(Rds2+RL), L} and V
Cs
=(Rds2+RL)I
o
.
Averaging over one
switching cycle,
Cin
Cout
RL
Rload
Rs
Vo
Vin
Cs
vC(t)
L
iL(t)
PN
Rds1
VPN
Figure 13. a) Equivalent sub-circuit.
C
i n
C out
RL
Rload
Rs
Vo
Vin
Cs
vC(t)
L
iL(t)
PN
Rds2
VPN
Figure 13. b) Equivalent sub-circuit.
V
Cs
=[D(Rds1+RL)+(1-D)(Rds2+RL)]I
o
or
V
Cs
=[D Rds1+(1-D)Rds2+RL]I
o
:=R
eq
I
o
.
The DC voltage across V
is independent of L, R
and C
. If
only the average load current is needed (as in average
current-mode control), this current sensing method will be
sufficient without any additional time-constant matching
constraint.
In peak current-mode control, the voltage ripple on C
is
used as the modulating ramp. The V
peak-to-peak
amplitude (denoted as
V
) directly affects the signal-
to-noise ratio of the PWM operation. Small
V
leads to
lower signal-to-noise ratio and more jittery operation.
Large
V
leads to more circuit (power stage) sensitive
operation. A good compromise is to make
V
Cs
~R
eq
δ
I
o
.
The above condition holds if the following time-constants
are made equal.
.
C
R
R
L
s
s
eq
If Rds1=Rds2, then R
= Rds1+ RL. For example, in the
application circuit, L=1.3μH, RL=1.56m
and
Rds1=Rds2=8m
, the time constant R
s
C
s
should be set
as 136μs. If C
s
=33nF, then R
s
=4.12k
.
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