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240
Revision 3.0
G
Core Logic Module
(Continued)
Offset 14h-17h
LAD_D0 — LPC Address Decode 0 Register (R/W)
Reset Value: 00080020h
31:23
22:19
Reserved.
LPC Game Port 1 Address Select.
Selects I/O Port:
0000: 200h
0001: 201h
0010: 202h
0011: 203h
Selected address range is enabled via F0BAR1+I/O Offset 10h[8].
LPC Game Port 0 Address Select.
Selects I/O Port:
0000: 200h
0100: 204h
0001: 201h
0101: 205h
0010: 202h
0110: 206h
0011: 203h
0111: 207h
Selected address range is enabled via F0BAR1+I/O Offset 10h[7].
LPC Floppy Disk Controller Address Select.
Selects I/O Port:
0: 3F0h-3F7h.
1: 370h-377h.
Selected address range is enabled via F0BAR1+I/O Offset 10h[6].
LPC Microsoft Sound System (MSS) Address Select.
Selects I/O Port:
00: 530h-537h
10: E80h-E87h
01: 604h-60Bh
11: F40h-F47h
Selected address range is enabled via F0BAR1+I/O Offset 10h[5].
LPC MIDI Address Select.
Selects I/O Port:
00: 300h-301h
10: 320h-321h
01: 310h-311h
11: 330h-331h
Selected address range is enabled via F0BAR1+I/O Offset 10h[4].
LPC Audio Address Select.
Selects I/O Port:
00: 220h-233h
10: 260h-273h
01: 240h-253h
11: 280h-293h
Selected address range is enabled via F0BAR1+I/O Offset 10h[3].
LPC Serial Port 1 Address Select.
Selects I/O Port:
000: 3F8h-3FFh
010: 220h-227h
001: 2F8h-2FFh
011: 228h-22Fh
Selected address range is enabled via F0BAR1+I/O Offset 10h[2].
LPC Serial Port 0 Address Select.
Selects I/O Port:
000: 3F8h-3FFh
010: 220h-227h
001: 2F8h-2FFh
011: 228h-22Fh
Selected address range is enabled via F0BAR1+I/O Offset 10h[1].
LPC Parallel Port Address Select.
Selects I/O Port:
00: 378h-37Fh (+778h-77Fh for ECP)
10: 3BCh-3BFh (+7BCh-7BFh for ECP)
0100: 204h
0101: 205h
0110: 206h
0111: 207h
1000: 208h
1001: 209h
1010: 20Ah
1011: 20Bh
1100: 20Ch
1101: 20Dh
1110: 20Eh
1111: 20Fh
18:15
1000: 208h
1001: 209h
1010: 20Ah
1011: 20Bh
1100: 20Ch
1101: 20Dh
1110: 20Eh
1111: 20Fh
14
13:12
11:10
9:8
7:5
100: 238h-23Fh
101: 2E8h-2EFh
110: 338h-33Fh
111: 3E8h-3EFh
4:2
100: 238h-23Fh
101: 2E8h-2EFh
110: 338h-33Fh
111: 3E8h-3EFh
1:0
01: 278h-27Fh (+678h-67Fh for ECP) (Note)
11: Reserved
Selected address range is enabled via F0BAR1+I/O Offset 10h[0].
Note:
279h is read only, writes are forwarded to ISA for PnP.
Offset 18h-1Bh
LAD_D1 — LPC Address Decode 1 Register (R/W)
Reset Value: 00000000h
31:16
15:9
Reserved.
Must be set to 0.
Wide Generic Base Address Select.
Defines a 512 byte space. Can be mapped anywhere in the 64 KB I/O space. AC97
and other configuration registers are expected to be mapped to this range. It is wide enough to allow many unforeseen
devices to be supported. Enabled at F0BAR1+I/O Offset 10h[9].
Note:
The selected range must not overlap any address range that is positively decoded by F0BAR1+I/O Offset 10h bits
[17], [14:10], and [8:0].
Reserved.
Must be set to 0.
8:0
Table 5-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers (Continued)
Bit
Description